OL3.NOV–Toshiba–RM
Rambus memories shipping from Toshiba
Toshiba is the first dynamic RAM maker to ship production Rambus DRAMs
built to the Rambus interface standard. For these RDRAMs, the company is
maintaining the promised 1.25 price ratio with standard page-mode DRAMs of
the same density. Toshiba and Rambus recently gave a multimedia
demonstration that exercised the 500-Mbyte/s data rate of the chips and an
application-specific IC containing the Rambus interface. This is the speed
originally promised (see Electronic Products, May 1992, p. 15; June 1993,
p. 50). Three super-VHS inputs were digitized and sent to a 1,280 x 1,024
x 18-bit monitor at full speed. The earliest market for these parts will
be graphics and video accelerator boards. These boards usually have an
ASIC that directly manages the frame buffer, whether video RAM or DRAM.
Since the Rambus interface is no bigger than a section of pad ring smaller
than the pins it would replace, redesign is minimal. Also, because the
board need only have four layers, fabrication is cheaper than the
multilayer boards needed for compact VRAM designs. For really intense
graphics, such as 3D workstations, four Rambus interfaces in parallel
provide a frame-buffer bandwidth of 2 Gbytes/s. This would only require
about 100 pins. Main memory is a tougher challenge for the new chips. As
long as the bulk of desktop systems run memory buses at 33 MHz, the Rambus
premium will not pay. In the next DRAM generation, when 16-Mbit parts are
the cheapest, the story will change. Entry-level PCs can be cheaper at the
outset if they can be configured with a minimum memory. With Rambus, a
minimum is one chip, 2 Mbytes with an 18-Mbit part. Using normal DRAMs, a
32-bit system would have at least two chips, and then only by using 1-M x
16-bit chips. If the cheaper 4-M x 4-bit chips were used, eight chips
would be required. The current part, the 512-K x 9-bit TC59R0409VK, has
access times of 48 ns read and 16 ns write on hits, that is, data already
in the sense amplifiers. With two 1-Kbyte sense-amp arrays, locality means
hits are not infrequent. For misses, initial access is 152 ns read or 120
ns write. Two cache lines are added for each RDRAM added to the system.The
method used to address individual chips allows n-way interleaving. When
one RDRAM is reloading its cache line after a miss, accesses to other
RDRAMs can take place on the same bus. If the application can predict the
next RDRAM it will access, it can send a dummy read in advance to load the
sense amps. The initial latency, or time needed to send the starting
address along the multiplexed bus, could be a problem for systems without
a secondary cache. However, on-chip primary caches are increasing, with
the current R4400 processor, for example, having 16-Kbyte caches. Along
with a caching algorithm that prefetches speculatively, such a cache size
might prove at least adequate. Toshiba expects to introduce a 0.5-micron
18-Mbit part, along with a 0.5-micron version of the ASIC interface, in
the first half of 1994. For information from Toshiba call Rick Horiuchi at
714-455-2000 or . NEC is expected to be next to market with an RDRAM,
with Fujitsu and Hitachi following. Brooktree has announced a license
agreement with Rambus, but has not announced related product plans.
–Rodney Myrvaagnes
CAPTION:
The Rambus technology strings 9-bit-wide memories on a special bus of
fixed geometry and impedance. It transfers data at 1 byte every 2 ns once
addressed.
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