Ref design enables BER testing

The 28G Bit Error Ratio (BER) Receiver reference design is suited for emerging high-speed protocols from 13 to 28 Gbits/s, including 100-Gbit Ethernet, 40G Differential Quadrature Phase Shift Keying (DQPSK), 14G Fibre Channel, and 100G Dual-Polarization Quadrature Phase Shift Keying (DP-QPSK). The reference design, together with a 12.5G BERT and a 28G high-speed test pattern generator, comprise a complete 28-Gbit/s test solution.

For test applications requiring clock recovery, the reference design provides a buffered copy of the high speed input data stream, which can be supplied to an optional clock recovery unit to generate a recovered clock. The ref design is based on an Inphi chipset of a 5081DX 50-Gbits/s 1:4 Demultiplexer, 25717CF 25-Gbit/s 1:2 Fanout, and 20709SE 20-Gbit/s 2:1 Selector. (E-mail company for price — available now.)

Inphi , Westlake Village , CA
Information 805-446-5100

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