Renesas and Intel talk processor architectures at ISSCC

Renesas and Intel talk processor architectures at ISSCC

The recent IEEE International Solid State Circuits Conference (ISSCC) in San Francisco had numerous interesting advancements among the 210 papers presented. In the area of processors Renesas/Hitachi and Intel described two of the most interesting new architectures.

Yoichi Yuyama of Renesas described a 45-nm heterogeneous multicore SoC with three types of processors targeting digital TV systems with IP networks. The chip has a 32-bit general-propose processing unit (VPU5) with sound and video processing, four dynamically reconfigurable 16-bit processing units (FEs), and two 1,024-way 4-bit matrix processors (MX-2). Three system buses provide the interconnect, and the device has two 2-Gbyte RAM interfaces. The three different granularities of the processing elements cut power consumption and provide optimum handling of different types of tasks. The IC takes only 3.07 W to yield 114.7 GOPS/s, running from a 1.15-V supply at 648 MHz.

Intel’s Nasser A. Kurd described the forthcoming Westmere family of 32-nm processors, which will come in two-core mainstream and six-core server configurations, both with Quick Path Interconnect yielding transfer rates up to 6.4 GT/s. The six-core version with a 12-Mbyte smart cache takes the same power as the previous-generation four-core device and has 1.17 billion transistors. The ICs have integrated memory and graphics controllers with two or three channels of LV-DDR3/DDR3 memory support at up to 1,333 MT/s. Overall, leakage accounts for about 23% of the total chip power. Power optimization includes an adaptive frequency and duty cycle system as well as power gates controlled by shift registers that can shut down cores and sections of L3 memory. The chips also have an Advance Encryption Standard (AES) engine. The processors are implemented as a flip chip attached to a 14-layer 40-mil-pitch OLGA package with an integrated heat spreader.

Jim Harrison