Repackaging Moore’s Law

Repackaging Moore’s Law

At the 2010 International Electron Devices Meeting in San Francisco, CA, last year, it was made very clear that continued scaling of CMOS to increase the functional density of ICs was becoming unfeasible. Keynote speaker Jim Clifford, general manager of operations at Qualcomm, noted that scaling was becoming too expensive, and Kinam Kim, president of Samsung Advanced Institute of Technology, in his keynote speech stated that CMOS scaling presents significant challenges in materials, performance, and capital outlay.

What appears to be a the growing consensus among IC companies is that, to keep increasing functional density in ICs, the answer lies not in silicon, but in packaging. Clifford said Qualcomm was turning to 3D through-silicon via (TSV) technology. Likewise, Kim said that 3D packaging holds the most promise for future devices.

Interestingly, the packaging technologies that the industry is now considering have their origins in the development of MEMS technology. These devices have particularly strict performance requirements that have led to development not only of TSV, but also wafer bonding and other technologies that are applicable to 3D packaging.

A recent article in Electronic Products, “Packaging faces a ‘perfect storm’” ( http://www2.electronicproducts.com/P-article-farc_packaging_feb2011-html.aspx), discusses this new direction ICs. It is making designers rethink the way devices are assembled and encapsulated to meet next generation requirements for electronics in applications ranging from consumer goods to military and industrial systems.