Researchers at Purdue University have developed a new technology, a custom logic family, that can be used to reduce the power needed by the CMOS battery-powered chip used in computers and other electronic devices to store data. The new technology can operate with a power supply down to near-threshold or sub-threshold levels to reduce the energy used by the CMOS, thus increasing battery life, said researchers.
(Image: Stock image, Purdue University)
“I saw a need for a way to reduce the power required by the CMOS, which is technology used in nearly all electronics. Our invention offers more efficient options than the current technology [Purdue’s CMOS gates are more energy efficient than standard CMOS gates.], and it reduces the power needed for the CMOS. This is particularly important as the world uses more electronic devices that are processing large amounts of data,” said John Lynch, who developed the technology, at Purdue’s College of Engineering. Lynch is a graduate research assistant in the lab of Saeed Mohammadi, a professor of electrical and computer engineering in Purdue’s College of Engineering.
“The technology reduces power in CMOS chips by enabling the operation down in the low-voltage mode,” Lynch told Electronic Products. “A servo is used to control both the p-type and n-type current in the digital gates in such a way as to control the delay.”
So how does it save battery life? Lynch said: “The energy spec is what is most important to save battery life, which is found by taking the power * time product. As the voltage is lowered, the energy reduction is proportional to the square of the voltage value. The devices are custom in that a terminal tying all the N-wells in the P-type transistors is brought out. The goal is to be able to design the gates in such a way as to use a digital methodology using synthesis, place, and route.”
Lynch compares this to today’s technology “when running at a given low voltage, the variation in the delays of the gate is reduced by an order of magnitude (>10×). As an additional benefit, the P-type transistors are >2 times smaller, which saves more power.”
In terms of battery savings, Lynch said the “best way to quantify the performance is to say that if both types of gates are running at the VDD causing the optimum energy level (for example, this might be VDD = 2.5 V), the timing will be 10× improved in how much the delay will vary over process. This variation is one of the biggest challenges in running in low-voltage mode in today’s technology, and our invention has greatly improved this problem.”
The researchers are looking for partners to continue developing and commercializing their technology. There is still more simulation work and silicon development to be done, said Lynch. “This work would be easy to continue if a partner was willing to fund the effort, for example in a development license for the patent.”
Researchers worked with the Purdue Research Foundation Office of Technology Commercialization to patent the technology.
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