Semtech Corp. has announced two new additions to its LoRa Core portfolio, a gateway baseband processor integrated with LoRa (SX1303) and a related LoRa Corecell gateway reference design that supports the fine timestamp feature. The SX1303 supports all of the features of the previous SX1302 baseband processor with the addition of the fine timestamp capability that enables time difference arrival (TDOA) network-based geolocation.
The LoRa Core family provides global LoRaWAN network coverage and targets a variety of applications including asset tracking, building, home, agriculture, metering, and factory automation. The portfolio consists of sub-GHz transceiver chips, gateway chips, and reference designs including the SX126x series, SX127x series, and LLCC68 transceiver chips, as well as the SX130x series gateway chips, legacy gateway reference designs, and the LoRa Corecell gateway reference designs.
Key features of the SX1303 LoRa Core chipset include:
- Provides accurate time of arrival information for each demodulated LoRa frame
- Fine timestamp is a nano second resolution value references to a PPS (pulse per second) signal
- Geolocation accuracy is around 75–150 meters depending on many different factors
- Size and pin-to-pin compatible with LoRa Core SX1302
- Featured for implementations leveraging the LoRaWAN protocol and worldwide sub-GHz bands
- Up to -141 dBm sensitivity with LoRa Core SX1250 Tx/Rx front-end
- Unique 64-bit serialized number for identification and security purposes
- Gateway offers lower power consumption and smaller size than legacy gateways
The new LoRa Corecell gateway reference design, with fine timestamp, is available for U.S., Europe, and China regions.
Semtech offers hands-on training to learn more about the LoRaWAN open specification through its LoRaWAN Academy.
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