Digital algorithms help provide high efficiency across the entire load line
BY DAVID WILLIAMS
CHiL Semiconductor, Tewksbury, MA
http://www.chilsemi.com
The onslaught of efficiency requirements for multiphase dc/dc voltage regulators (VRs) has caused a major shift in VR solutions throughout the computing industry. While such computing industry specifications as Climate Savers or Energy Star do not specify exact dc/dc efficiency requirements, they make it abundantly clear that efficiency from 20% to 100% load needs to constantly improve. Major OEM customers, especially in the server industry, are demanding even higher efficiency levels than industry forums are proposing. To shape the efficiency across the CPU’s entire load, as well as the memory, CHiL Semiconductor has implemented several digital algorithms in its digital power management IC families. CHiL’s digital algorithms combine to create a shaped efficiency curve, which results in high efficiency across the entire load line.
Efficiency evolution and shaping
The efficiency of VR solutions, whether for CPU or memory on servers, or for graphics controllers on graphics boards or in high performance computing (HPC) applications, has evolved over time as a function of cost and size. Key factors driving the need for higher efficiency include total cost of ownership (TCO) and the concern for greener solutions. Figure 1 , showing multiphase systems converting 12 to 1.2 V, highlights the evolution of efficiency in servers from initial levels in 2008 to shaped efficiencies available in 2010.
Fig. 1. Evolution of VR efficiency in server systems.
Initially, efficiency and TCO were not a concern, and efficiency typically peaked near the 88% range. At lower currents, in idle states, the efficiency dropped off due to the switching losses of multiple phases. The introduction of the power savings indicator (PSI) in 2008 allowed VR solutions to turn off all but one phase at lower load currents, raising the efficiency in idle states. The efficiency over various operating modes, especially in servers where 20% to 100% operation is the most important, was still quite low.
Solutions that strived to achieve higher efficiency would use discrete MOSFETs (metal-oxide-semiconductor field-effect transistors) with lower RDS(on) (defined as the resistance when the device is in saturation) in the solution, driving the higher load efficiency to higher points, costing efficiency at lower loads due to increased drive losses. Integrated solutions, whether monolithic or multi-chip, reduced parasitic losses and increased efficiencies at the low range.
The shaped-efficiency-curve created by CHiL’s digital algorithms results in high efficiency across the entire load line. The high efficiency is accomplished using two primary methodologies – dynamic phase control and variable gate drive.
Dynamic phase control
Dynamic phase control (DPC) is the fast, controlled management of phases in a multiphase VR solution, combining the shedding of phases during average current, and extremely fast and controlled addition of phases during peak or transient currents as well as average current.
Phase shedding, as it has been called, is quite easily implemented in VR solutions. By simply measuring the average current and reducing the number of operating phases, switching losses can be mitigated. While a simple concept, in the past it has not been effectively implemented in servers because of the need to respond to large increases in current due to CPU, memory, or GPU transients. Adding phases slowly is an unacceptable solution because it results in the saturation of inductors, or will require an excess of bulk capacitors on the output of the VR solution to hold the voltage while the phases are added. CHiL’s non-linear approach to adding phases overcomes these issues.
A six-phase server VR solution using DPC is shown in Fig. 2, where the load current is changed at high speed from 105 to 30 A and back to 105 A. This example used no more bulk capacitors than is required for normal transient responses. The response to a load release is a controlled dropping of phases one at a time to reach the ideal efficiency operating point at 30 A, which in this example is two phases. The response to the load step increase is very fast controlled turn-on of the phases to ramp the current in the inductors and drive the current to the load. A careful examination of the timing of the 4 additional phases shows that they are not turned on at exactly the same time. The algorithm used manages the timing frequency and pulse width of each phase turning on. This minimizes overshoot as well as such common analog problems as ringback, the overshoot caused by driving too much current into the output stage too quickly.
Controlling this ability to shed phases to save power and to add phases to respond to transients is the only way practical server solutions can realize the shaped efficiency shown in Fig. 2 .
Fig. 2. Dynamic phase control response to changing load currents.
Variable gate drive
A second mechanism to achieve higher efficiency across the load is variable gate drive (VGD), which is managing the gate drive to the MOSFETs or powerstage device during different load currents. Normal server solutions usually choose a gate drive voltage that is either 12 V, 5 V, or an intermediate voltage that is chosen to optimize the RDS(on) at only one operating point. Some systems will toggle between 12 and 5 V at lower currents. No one fixed gate drive voltage is ideal. CHiL has implemented a programmable gate drive algorithm that allows the user to vary the gate drive voltage from any point at low currents to any other point at higher currents. A typical example may vary the voltage from 5 to 9 V. 5-V operation at lower currents save significant gate drive losses while 9-V operation at high loads reduce RDS(on) to its minimum value while not overdriving the MOSFET’s 12-V operation.
The effects of VGD in a low cost four-phase desktop design are shown in Fig. 3. Dynamic phase control, discontinuous mode and PSI operations are turned off to show the effects of varying the gate drive in the system. The efficiency is improved by 10% at 10 A, and by 1% to 3% at higher currents.
Fig. 3. Dynamic phase control response to changing load currents.
Dynamic phase control and variable gate drive algorithms increase efficiency
Implementing the Dynamic Phase Control and the Variable Gate Drive algorithms as shown in this paper result in a shaped efficiency that increases efficiency across the entire load. Likewise, these algorithms are independent of any particular power devices or gate drivers, so any VR solution can improve the efficiency above that of the existing device, no matter which device is used. ■
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