SoC debug tool expands verification methods

The Verdi automated debug system for SoC design has expanded its verification interoperability by supporting the Universal Verification Methodogy (UVM). The software adds UVM source code and transaction recording capabilities to its existing HDL debug platform, making it easier for engineers to visualize complex SystemVerilog testbench structures of SoC devices.

Key features include a tabular spreadsheet view for highlighting and filtering of transactions, easy-to-use class browsers for navigating testbench hierarchy, and automated tracing through source code. (One-year subscription license, $14,000a available now.)

By Jim Harrison

SpringSoft , San Jose , CA
Sales 408-467-7888
www.springsoft.com