Software interface standard gives new framework
CMSIS is an easy-to-use programming interface for Cortex MCU-based real-time systems
BY REINHARD KEIL
ARM, Plano, TX
http://www.arm.com
Microcontrollers based on the ARM Cortex-M3 processor are becoming very popular in the industry. The recent introduction of the Cortex-M0 processor allows for more power- and cost-effective devices. Cortex-M processors are software compatible, and together with the Cortex Microcontroller Software Interface Standard (CMSIS), simplify porting of software.
The general-purpose MCU segment is one of the most fragmented markets in the electronics industry. The many microcontroller architectures frequently have a long history — most 8- and 16-bit architectures were invented more than 20 years ago. Over the years, these architectures have been reshaped several times to meet the needs of today’s demanding applications. To aid CPU performance, a math accelerator or a hardware CORDIC (cordinate rotation digital computer) are sometimes added.
Since no peripheral and interface standards exist, programmers must invent solutions over and over again for the same basic problems and adopt existing software algorithms to new hardware. In such environments object-oriented programming rarely can be used. Generic software components that are common in the PC world are not available, and the lack of programming standards limits software reuse.
Instead, silicon vendors must provide free software frameworks for new devices tailored toward specific applications. This slows the introduction of new devices and significantly increases development costs.
Debug shortcomings
A shortcoming of today’s 8- and 16-bit microcontrollers is the proprietary debug technology that is integrated into many of the devices. In many cases only tests with breakpoints are possible. Data trace capabilities required for the dynamic analysis of running applications are not always available. This, together with the higher expectations for modern products, is causing software development for deeply embedded applications to become more and more expensive.
These symptoms prevent real innovation. When the standard platform of the PC became available, many new software products appeared on the market and new businesses around such solutions became successful. MCUs could use such a standard platform as well.
The Cortex-M3 processor (see Fig. 1 ) includes a 32-bit CPU and a wake-up interrupt controller (WIC) for low-power operation. Together with the nested vector interrupt controller (NVIC), the processor delivers very fast interrupt response times, with multiple priorities.
A debug access port, combined with a serial-wire viewer and embedded trace macrocell (ETM), provides the extensive trace capabilities for non-intrusive software verification of a running system. The MCU’s memory protection unit enables reliable software implementations and RTOS kernels.
Fig. 1. Components of the Cortex-M3 processor.
Software interface standards
Soon to be expanded to include future Cortex processor cores, the CMSIS addresses the challenges faced when various software components are deployed to the actual physical processor. It is defined in close cooperation with various silicon vendors, and for wide acceptance in the industry, software vendors such as IAR, Keil, Micrium, Segger, and Tasking are also involved.
Fig. 2. Structure of the CMSIS abstraction layers.
This collaboration has resulted in an easy-to-use and easy-to-learn programming interface. CMSIS provides a common approach for interfacing to peripherals, RTOSs, and middleware components. The CMSIS is compatible with several compiler implementations, including GCC, and provides the following two software layers shown in orange in Fig. 2 .
Peripheral Access Layer (CMSIS-PAL) contains name definitions, address definitions, and helper functions to access processor core registers and device peripherals. It introduces a consistent way to access core peripherals and exception/interrupt vectors. It provides a standard system startup function. CMSIS-PAL also defines a device independent interface for an RTOS kernel and data trace channels for RTOS kernel-awareness in debuggers and simple printf-style debugging.Middleware Access Layer (CMSIS-MAL) provides common methods to access peripherals for the software industry. The MAL is adapted by the silicon vendor for the device-specific peripherals used by more complex middleware components such as communication stacks. It is currently in development, and we expect that IAR, Keil, Micrium, Segger, and other middleware vendors will start shipping CMSIS-MAL-compliant components in the second half of this year.
The CMSIS is not another complex software layer that forces silicon vendors to produce identical features. The CMSIS-PAL defines common methods to program peripherals.
The device peripherals such as I/O Port, Timer, PWM, A/D, D/A, etc. can have different performance and functions. The CMSIS does not prevent direct hardware access since the peripheral registers of a device can be still accessed directly.
The CMSIS does not require immense resources, and the CMSIS-PAL requires fewer than 1 Kbyte of code and just 4 bytes of variable space. The CMSIS-MAL is only required to interface to standard middleware (sophisticated communication stacks) and a hardware abstraction layer (HAL) is common in such components. CMSIS-MAL replaces, therefore, a proprietary middleware HAL and cannot be considered additional overhead.
The CMSIS provides many benefits such as a consistent software framework and a proven software layer. This enables easy deployment of template code and program examples across supported compiler vendors.
The Cortex-M3 processor, along with its core peripherals, is consistent across the various silicon vendors and ARM provides a common documentation for these components. Together with the CMSIS, this will allow generic introduction books that are not vendor or device specific. Over time, we expect a reduction of the learning-curve for application programmers that have previous experience with Cortex-Mx devices from other vendors and now start using a new Mx device.
CMSIS consistency
Since the CMSIS layer is identical across all compiler vendors, no adaptations are required when changing a tool chain. It provides standard interfaces that can be used by many silicon and middleware partners and reduces project risks since a CMSIS interface maybe pre-verified and certified. Once the standard is widely adopted, user source code that uses CMSIS interfaces is easier to understand and, therefore, easier to verify.
Historically, industries use standards to improve product quality and enable component and cost sharing across projects. In practice, such standards achieve wide acceptance because the synergistic effects provide significant benefits to the user community. The electronics industry is full of such standards, but the deeply embedded microcontroller market is still using many proprietary CPU architectures, which has prevented from the introduction of efficient software standards.
A standard processor such as the Cortex-M3 allows for not just reusing the same development tools for many projects; together with the CMSIS, it also reduces development costs since software components can be shared across projects more easily. Silicon vendors can focus more on device features and peripherals, rather than creating a proprietary software layer and basic interface routines. The common programming techniques introduced by CMSIS simplify long-term software maintenance since applications that are using CMSIS interfaces can be easily understood even by new team members. ■
For more on software for microprocessors, visit http://www2.electronicproducts.com/Software.aspx.
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