HL6.DEC–Texas Instruments–rm
Sparc for low-end workstations
Simple workstations will top 486-class performance, perhaps at lower
cost
A highly integrated but relatively simple Sparc chip, the TMS390S10
microSparc is a joint effort of TI and Sun Microsystems, like the
elaborate but hard to make superSparc. The 15 x 15-mm chip has only 800,
000 transistors, compared to 3,100,000 in the 15.9 x 15.9-mm superSparc.
The yield is said to be very high, in contrast to the superSparc, and the
chips are available to everyone. In addition to a Sparc integer unit, the
chip incorporates a simplified floating-point unit, separate 4-Kbyte
instruction cache and 2-Kbyte data cache, Sparc reference MMU,
configurable dynamic-RAM controller, glueless Sbus interface supporting
five slots, and JTAG boundary scan. A minimum system needs a crystal,
memory, and whatever peripherals the target market needs. Without
secondary cache, systems based on microSparc are intended to compete with
PCs for commercial applications, rather than engineering. However, it is
completely Sparc 8 compatible and could run any Sparc software. Both
caches are 32 bits wide, physically tagged, and direct mapped. A write
buffer is one double-word deep. The data bus to main memory is 64 bits
wide, with one parity bet for each 32-bit word. The Sbus controller
allows 2-, 4-, 8-, and 16-byte bursts, and runs at 25 MHz when the CPU
clock is 50 MHz. TI projects SPECint 92 of 20-23 and SPECfp 92 of 15-18.
The typical power dissipation is 3.5 W. ($1,000 ea/sample, $179 ea/10,
000–available now.) Texas Instruments Inc. Dallas, TX Semiconductor
Group (SC-92093) 214-995-6611, ext. 3990
CAPTION:
This Sparc microprocessor in a thin TAB package, with 10-mil spacing,
could fit in portable computers.
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