HL5.OCT–RM–Altera
SRAM-based FPGAs offer predictable timing, cascadable counter sections
FPGAs join the company's EPLD families, all using the same design
software
Yet another FPGA architecture rears a not-too-ugly head just when you
thought it was safe to settle on something already out there. Altera has
added a static RAM-based array family, the FLEX 8000 family, to its PLD
line, with five sizes ranging from 4,000 to 24,000 usable gates, and from
452 to 2,252 flip-flops. Predictable delays across the chip, normal for
sum-of-products PLDs like MAX 5000 and MAX 7000, are not usual in array
architectures. FLEX has two-level granularity, with small cells grouped in
blocks of eight. The fine cell–called logic element or LE–combines a
four-input lookup table with a flip-flop (see diagram inset). LEs are
strung together by a cascade chain and a carry chain within the block of
eight–called logic array block, or LAB–and extended from LAB to LAB
throughout a row. LEs within an LAB have a 1-ns interconnection with each
other. Cascade and carry links add 1 ns each, giving counters of any
length adding 1 ns/bit. The delay through an LE is 5 ns, which is
comparable to that of Xilinx parts. The cascade line makes logic functions
with more than four inputs possible, again at a penalty of 1 ns for each
block of four inputs added. The LABs are linked throughout the chip by
row and column lines that all run from edge to edge. I/O cells are on the
ends of these routing channels (see diagram). LAB outputs drive horizontal
wires directly. Some inputs come from horizontal wires, some from
vertical. Connections from vertical to horizontal are made in the LAB at
the corner. LEs whose I/O lines are connected inside the LAB make lines to
the routing channels available for corner connection. LEs in different
LABs on the same row have a 6-ns interconnect delay. If they are on
different rows, one column adds 3 ns, for a maximum delay of 9 ns. These
fixed delays contribute to the predictability of designs. I/O cells also
have configurable flip-flops. They also have individually programmed slew
rates. Input delays are about 2.5 ns. Outputs, including combinatorial and
register delays, come to about 5 ns. The first chip to be sampled is the
EPF81188, with 1,188 flip-flops and 180 I/O cells. The second chip, the
EPF8452, due early next year, will be the smallest, with 116 I/O and 452
flip-flops. The largest member of the family, the EPF82252, with 236 I/O
and 2252 flip-flops, will see daylight in 1994. Like Xilinx LCAs, FLEX
chips can configure themselves from byte-wide or serial EPROMs at reset,
or they can be configured by a microprocessor. The SRAM configuration lets
them be reconfigured on the fly for different tasks. The most recent
version of the company's proprietary design software, MAX+PLUS II, can
take design input independent of final architecture, then simulate and
synthesize the design in single EPLDs, MAX 5000, MAX 7000, or FLEX 8000
devices. It can partition a large design over multiple chips of a single
architecture only. The software accepts EDIF files from any standard EDA
package. (EPF81188, $495 ea/100–samples now.) Altera Corp., San Jose,
CA Sandeep Vij 408-894-7177
CAPTION:
Any logic element in the Flex architecture can connect to any other, with
at most a single row and single column of routing. The maximum intercell
delay is 9 ns. The individual cell in the FLEX architecture (inset) has a
four-input lookup table and a flip-flop. Daisy-chained carry and cascade
links make wider functions and longer counters possible, all with
predictable penalties.
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