Synchronous clock suits SDH, SONET networks

Fully compliant with ITU-G.813 and Telcordia GR1244 and GR253, the STC5270 synchronous clock solution accepts two reference inputs and generates two independent synchronized output clocks. The clock generator includes a DPLL (Digital Phase-Locked Loop), which may operate in the freerun, synchronized, and holdover modes.

Features include a standard SPI bus, a programmable loop bandwidth, from 0.1 to 103 Hz, and a hold over accuracy of better than 0.1 ppb. The device is available in a TQ100 package and operates with an external 20-MHz OCXO or TCXO. ($10 ea—available now.)

Connor-Winfield , Aurora , IL
Information 630-851-4722

http://www.conwin.com