Test-bench generation tool simplifies IC design

Test-bench generation tool simplifies IC design

TestBencher Pro VHDL and Verilog system-level test-bench generation software is said to dramatically simplify the process of creating and applying random bus transactions to RTL and gate-level IC and SoC design models. It includes an updated version of the BugHunter Pro graphical HDL debugger and improved support of ModelSim and Incisive simulators on Windows and Linux platforms.

The new version eliminates many of the manual coding steps that were necessary to create a test bench that applies a set of weighted-random transactions with constrained-random input data to a model under test. The user draws timing diagrams representing protocols for the test bench's transactions with time and state variables to indicate input data. TestBencher supports both protocol checking and scoreboarding of transaction payloads using graphical constructs in the timing diagram. (Node-locked Unix version, $25,000 — available now.)

By Jim Harrison

SynaptiCAD , Blacksburg , VA
Sales 540-953-3390

www.syncad.com