Test bits

Economical DFT

As beneficial as design-for-test methodologies like boundary scan arethey not only help ensure the quality of the delivered end-product, but they can considerably cut manufacturing test timethey often have a big drawback: they require extra circuitry and development time, an overhead that designers want to avoid so they can keep design and parts costs as low as possible. That’s why the IEEE P1581 working group is looking to define a low-overhead DFT methodology for memory devices, one that can support both board- and system-level test.

A key part of the concept is that the DFT circuitry need not be used solely for test, nor would the outside controller be a test-only resource. In fact, the circuitry could be slaved to an external resource such as an in-circuit tester or BIST circuitry, and optionally it could allow access to on-chip device ID data and built-in self-repair circuitry. Further, the test logic would be simple and permit fast test execution, and would do so without extra device pins.

The working group is looking for input from interested parties. Anyone can download a white paper, An Economical Alternative to Boundary Scan in Memory Devices, from http://grouper.ieee.org/groups/1581/documents/P1581_White_Paper_a20070103.pdf to read an overview of the proposed standard’s various technical details.

After reading the paper, if you wish to comment on the proposal, you can contact Heiko Ehrenberg of GOEPEL Electronics (Austin, TX), who chairs the group, at
. It’s also possible to sit in on teleconference meetings or become a participating group member; Ehrenberg will notify you of the next meeting and provide phone-access info.