Texas Instruments driving development and ratification of new IEEE 1149.7 standard to slash space and cost for

Texas Instruments driving development and ratification of new IEEE 1149.7 standard to slash space and cost for embedded systems

New two-pin compact test and debug solution reduces strict pin-count, package size and power constraints

HOUSTON (September 2, 2008) – As chips add new functionality and system designs evolve away from boards and toward multi-chip system-on-chip (SoC) architectures, developers of handheld and consumer electronics are faced with stricter pin and package constraints. Texas Instruments Incorporated (TI) (NYSE: TXN), a key member of the IEEE working group, announced that it is driving the ratification of the IEEE 1149.7 standard, a new two-pin test and debug interface standard that supports half the number of pins of the IEEE 1149.1 technology, allowing developers to easily test and debug products with complex digital circuitry, multiple CPUs and applications software in products such as mobile and handheld communication devices. In addition to leading the development and adoption of the new IEEE 1149.7 standard, TI is also working with Freescale Semiconductor, Intel Corporation, Lauterbach Datentechnik GmbH, IPExtreme, ASSET InterTech, Inc., Corelis and GlobeTech Solutions to refine and identify implementation challenges, ensuring a streamlined and robust solution is ready for industry wide adoption. For more information, please visit: www.ieee.org or www.ti.com.

The IEEE 1149.7 is a complementary superset of the widely adopted IEEE 1149.1 (JTAG) standard that has been in use for more than two decades. Scheduled for ratification in early 2009, the new standard acts as a port into embedded systems for device manufacturing, testing and software development during system development. In addition to maintaining compatibility with IEEE 1149.1, the new standard improves debug capabilities and reduces SoC pin-count requirements. It also standardizes power-saving conditions, simplifies manufacturing of multi-chip modules and stacked die devices, and provides the ability to transport instrumentation data.

The IEEE 1149.7 test and debug technology will be a milestone for the electronics industry by allowing engineers to easily update their current designs to the new standard while preserving investments and compatibility with existing IP modules and tooling,” said Stephen Lau, emulation technology product manager, TI. “TI is joined by leading companies such as Freescale, Intel and STMicroelectronics in the industry-wide adoption and integration of this technology into our products.”

Maintaining compatibility with fewer pins

Since a majority of today’s systems integrate multiple ICs and often have stringent size constraints, reducing the number of pins and traces will help designers meet their smaller form factor goals and allow for additional functional pins and/or lower package cost. Compared to the four pins reserved for IEEE1149.1, the IEEE 1149.7 uses only two pins to handle clocking, control and data I/O. The lower pin-count configurations simplify stacked-die configurations and decrease costs by eliminating the need for additional pins, thus facilitating smaller device form factors. Compatibility with existing IEEE 1149.1 devices and IP allows designers to smoothly transition to IEEE 1149.7 without incurring additional costs. For more details, please visit http://tiexpressdsp.com/wiki/index.php?title=IEEE_1149.7

“Reducing pin count is an important technology to enable advanced mobile devices,” said Rolf Kühnis, Nokia, chairman of the Mobile Industry Processor Interface (MIPISM) Test and Debug working group. “IEEE 1149.7 is a standardized, reduced pin interface which is compatible with existing technologies and addresses multi-chip debug challenges. This is why IEEE 1149.7 is recommended in the MIPISM test and debug specifications.”

New functionality addresses emerging challenges

The new IEEE 1149.7 standard provides powerful extensions to the IEEE 1149.1 in order to address SoC architecture challenges, such as scan performance in cards with multi-core devices, power domains, varied device connection topologies and background data transfers. To achieve higher performance for multi-core applications, the new standard offers a chip-level bypass mechanism to shorten scan chains, greatly improve the debugging experience. For power sensitive applications, especially handheld devices, four power-down modes are provided in IEEE 1149.7, assisting engineers during board and chip testing and applications debugging. The introduction of a star topology to complement the standard serial topology enables designers to easily manage multi-chip architectures since the physical inter-device connections are greatly simplified. Background data transfers provide an industry standard method to send instrumentation data, increasing visibility into SoC devices.

Building on TI’s test and debug expertise

As a key contributor to the development of the original JTAG test technology, the new IEEE 1149.7 standard builds on TI’s extensive scan-based expertise. For the IEEE 1149.1 standard, TI pioneered scan-based emulation and the XDS series emulators, reducing debugging costs and difficulties by communicating directly with the processor for non-intrusive visibility into all on-chip functions. For IEEE 1149.7, TI builds upon its expertise and experience in creating compatible products to deliver new capabilities with fewer pins and without disrupting the current ecosystem that is based on IEEE 1149.1. The IEEE 1149.7 is expected to be ratified in 1Q 2009.