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The RM48L952 device is a high-performance microcontroller family for safety systems.
The safety architecture includes: dual CPUs in lockstep, CPU and memory Built-In Self-Test (BIST) logic, ECC on both the flash and the data SRAM, parity on peripheral memories, as well as loopback capability on peripheral I/Os. The RM48L952 integrates the ARM Cortex-R4F Floating-Point CPU, which offers an efficient 1.66 DMIPS/MHz and has configurations that can run up to 220 MHz. The device supports the little-endian [LE] format. It has 3MB of integrated flash and 256KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input for all read, program, and erase operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word and double-word modes. The RM48L952 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit analog-to-digital converters (ADCs) supporting up to 24 inputs.
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