The LatticeECP3 FPGA family

Product of the Year winner ECP3 mid-range FPGAs from Lattice Semiconductor distinguish themselves in a couple of critical areas. First, low power fully active power for the 149 K-LUT device is only about 1.5 W. Second, they have up to 16 3.2-Gbit/s SerDes with 10-GbE XAUI jitter compliance, and these fast ports take only 90 to 110 mW each.

Engineers have faced a binary choice when selecting an FPGA: either a high-end full-featured device that was expensive and took a bunch of power, or a low-end device that imposed significant limitations on features and performance. Many designs don’t need 12-Gbit SerDes, but they must have some fast I/O as well as high-performance signal processing and memory capabilities. The LatticeECP3 covers midrange applications really well.

The Lattice design team concentrated on what is most important for high-volume applications: SerDes, I/O, memory, and DSP. They broke ranks with the notion that bigger and faster is always better. Instead, they had the discipline to design intelligently and purposefully for low cost and power without compromising robust, balanced functionality.

Challenges for the design

The overarching challenge that the team had to take on was to combine low-power, low-cost, high-speed embedded SerDes and high-speed source synchronous I/Os. To gain a low-power edge, innovative circuit design approaches were required in nearly all areas of the product design. This was especially true in the core logic fabric and the embedded SerDes block. And, to keep the product low cost, the team had to overcome two major hurdles: they had to have the smallest die size in the industry and also had to deliver a high-speed 16-channel 3.2-Gbit/s SerDes capability in low-cost wirebond packaging.

For high-speed SerDes in wirebond packages, the team had to perform detailed design simulations that comprehended the entire channel model (die, bond wires, package, board traces, connectors, etc.) and optimize both the circuit design and the package design for high signal integrity and minimum signal loss. The families’ high-speed source synchronous I/Os was one of the most challenging aspects of the project, as it spans the areas of circuit design, package design, applications, board design, and IP design. A cross-functional team from all of these areas worked to develop real-world bench evaluation capabilities in order to validate the product’s capabilities.

Jim Harrison