As today’s computing applications become increasingly more complex, developers are constantly seeking high-performance SoCs that not only provide low system cost, but add the flexibility of programmable logic. While architectures up to this point have addressed some of these needs, Altera’s Chris Balough states “History has shown us that every architecture reaches a limit.” With that in mind, Altera has aimed its efforts towards looking beyond the current limitations to create a line of SoC FPGAs, which boasts impressive performance specifications and flexibility to meet the high degree of system requirements of today’s applications. However, not all SoC FPGAs are created equal.
EEWeb spoke with Balough to elucidate this new field of embedded architecture.
What are the benefits that come from combining an FPGA with an SoC?
At a fundamental level, this combination is a classic integration benefit. If you can do on a single monolithic die that which was previously done in two die, your solution will be lower cost, lower power, less area, and will eliminate the delay times across the two-chip scenario—leading to high levels of performance. This value proposition is ideal for people who have adopted FPGAs, which have become extremely widespread now and happen to use a comparably classed processor. This is a large market for us, and we help take what the users are doing at the system level and make it better, which allows Altera to service more of the board. There is also a second, emerging benefit of this combination, which uses them as an integrated computing platform.
Could you explain more about the devices’ use as an integrated computing platform?
People are beginning to think about SoC FPGAs not as two separate chips with two separate development environments that happen to inhabit the same piece of silicon, but as an integrated computing platform. In our view, we see this as the next wave of embedded computing architectures and topologies. The evolution started many years ago with a single processor, like the x86. From there, the goal was to find more ways to leverage Moore’s Law and do architectural enhancements to increase performance continuously. As the needs for processing continue to grow, the evolution moved to multi-core processors because the industry ran into a dead end in terms of being able to crank up the performance of a single core.
There are still limitations with homogeneous multi-core computing, and what started to emerge here recently was this idea of heterogeneous multi-core computing. ARM coined the term big.LITTLE, which means that they will provide developers different kinds of processors that can be used together. The big, fast, power-hungry processors can be used only for the workloads that need it, and smaller, more power-efficient processors will be for the more manageable types of workloads. This is the most power-efficient and area-efficient combination by the idea of heterogeneous multi-cores.
History has shown that each architecture reaches a limit. Our projection is that the next phase, which we are calling fine-grain heterogeneous computing, will use FPGAs as accelerators in data centers, as well as in many embedded applications. This will use the capacity and the innate capabilities of the FPGA to be fine-grain on specific functions that need to be accelerated or computed, and coupling that with the traditional flexible compute idea of a traditional processor. We see that combination as really profound for the next stage in computing.
What differentiates Altera’s SoCs from the competition?
Both Altera and Xilinx launched into the SoC FPGA category at the 28-nanometer node, which came out in 2012. Increasingly, our customers are now thinking of this in more traditional application processor terms—they are thinking of us as a long-term application processor vendor. They are looking at us as the ones that will take care of the software application code, which is often the crown jewel for our customers.
The main tagline that we use is “architecture matters.” We have done a very detailed comparison of these two roducts and we have published an in-depth white paper on the silicon and development software. There are a number of items, as you go from 50-thousand feet down to a much closer view, where we think we got it right from an overall device and total solution architecture standpoint. One example of that is we support 32-bit-wide DRAM with error correction code (ECC) on all of our devices, and our competitors do not. In many embedded applications, it’s just unthinkable that you wouldn’t have the ability to have ECC memory, especially in reliability-intensive markets like automotive and industrial control.
A good example of software differentiation is how we have stuck with open standard, which our customers really value. We didn’t create our own development tool—we decided to partner with ARM and develop their flagship DS-5 software and turn it into the Altera edition of the DS-5. With our kits, the customer gets ARM’s DS-5 full development software tool as a part of the kit experience. We partnered with ARM to innovate what we call FPGA-adaptive debug, which allows the debug environment that is native to DS-5 to connect with the FPGA debug environment so that you can really synchronize the debug sessions.
The portfolio level is becoming a dominant way of looking at things, and that is where the differences between our competitors and us become especially significant. Altera is in this for the long haul in a big way. We see this as a substantial disruption in the programmable logic business. After 28-nanometers, we went all in and invested in a full SoC FPGA offering at 20-nanometers in our Arria 10 family. For our 14-nanometer family, we are all-in with the Stratix 10. Furthermore, we have also upgraded to the 64-bit processor in that family. When we present at a portfolio layer, we have a very strong story to tell because we have the best products at 28-nanometers that are in the cost-sensitive range. At the advanced 20-nanometer node, we are the only ones in the game if you want a 20-nanometer mid-range SoC FPGA. We are also the only game in town if you want the most advanced technology at the highest densities. Above one million logic elements (LE), our competitors have no stated plans to be in the business. We are the technology leader at 14-nanometers at the high density and we are the portfolio leader with an all-in game plan at 28- and 14-nanometers.
Let’s talk about Stratix 10 and the switch to the Intel Tri-Gate process. Could you comment on that switch and the benefits you have seen as a result?
As you can imagine, that wasn’t a light decision—this switch was considered for a long period of time. Furthermore, we have a deep, lasting relationship with Taiwan Semiconductor Manufacturing Company (TSMC), so we really only moved with careful study. So far, it is living up to our expectations. For one thing, Intel is so advanced and we have historically only rolled out products very early in the process technology life—we are one of the firsts to be on the process technology and we are taping out right at the time that it is fully qualified for production. Intel was in volume production of their 14-nanometer Tri-Gate process since last year, which is a very new experience for us. They have shipped billions of these advanced transistors in production, and everyone else has shipped zero. We inherited a very mature production process, and that is significant. Since they are on a true 14-nanometer process, we are able to announce 5-million LE devices, which is five times bigger than the largest monolithic FPGA that has ever been produced. The performance, density, and capacity we can achieve on these is where you see the true value of the 14-nanometers.
Additionally, we inherited some amazingly advanced packaging technologies like the embedded, multi-die interface bridge—or the EMIB technology—that we are using to deploy the Stratix 10 and the transceiver technology. That allows us to decouple the transceivers and use existing, solid 20-nanometer transceiver tiles, which are extremely high performance, and couple that with a digital FPGA device. This allows the device to be less limited on what would be a typical interposer-based multi-chip approach. With the EMIB technology, you are no longer reticle limited. You can build your base-FPGA to the full reticle size and get rid of all the transceivers, which allows you to basically fill the reticle with FPGA gates. The combination of the 14-nanometer process and the packaging technology allows us to deliver a knockout technology winner.
What markets or industries will benefit most from Altera’s SoC FPGAs?
We deployed this three-generation portfolio, so we expect to see a substantial adoption of SoC FPGA technology in all of our end markets. The first generation at 28-nanometers was tuned a little more towards the industrial automation and automotive area. The Arria 10 generation is geared more towards wireless infrastructure, storage, test, medical, and high-end industrial automation. The Stratix 10 family is what takes us into heavy-duty data center and computing industries, as well as military and defense and wire communications.
The Altera SoC Developers Forum (ASDF) is coming up on October 14th . What are your goals with this forum and do plan on getting developers not only educated, but engaged with SoC FPGAs?
We have come a long way on that already. For example, for 28-nanometers, we have 24 different production-qualified operating systems. We have already tremendous engagement and momentum in the OS ecosystem space with a number of design partners and development kits. The ASDF is made to be an amplifier and accelerator because what we haven’t done yet is get everyone together for a single-purpose SoC FPGA-focused event.
In your view, what would be the main reason to attend the ASDF?
If you are a developer, this is a can’t-miss event because this is going to be a single day of the most in-depth exposure you can get to the very latest technology from Altera and our industry-leading technology partners such as ARM, Lauterbach, MathWorks, Terasic, Wind River Systems, Arrow, and many more. There will be technical tracks that will highlight some of the newest case studies and tips and tricks on how to accelerate your development and be more productive. There will also be highlights on what is coming next in the industry.
For more information about the ASDF event, visit: https://www.altera.com/events/northamerica/altera-soc-developers-forum/overview.highResolutionDisplay.html
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