The path to power-efficient designs

How to enable chip-package-system design convergence with modeling technology for every step of the design process

BY AVEEK SARKAR
VP Product Engineering & Support
Apache Design
www.apache-da.com/

The shift in the way people communicate and use computers over the last few years has been drastic. Some key changes include the prevalence of mobile Internet-connected devices (smartphones and tablets), the move to cloud computing using larger centralized data centers, and the increased use of electronics in automobiles for guidance, entertainment, and safety control systems.

The shift has also changed the requirements for electronic system designs with a focus on power-efficient computing. The challenges that SoC designers face is enormous in delivering electronic systems that provide the required performance, meet all specifications and tests — and are done for the least possible cost.

Fig. 1: Designer engineers today have access to a comprehensive suite of solutions to simulate the IC, the package, and the PCB individually and in a holistic manner.

As efficient computing increases and ICs are fabricated using process technologies that are more sensitive to variations in temperature, accurate modeling and prediction of chip-level, package-level, and system-level thermal modeling become a necessary design step. Engineers can use chip-package-system design convergence with modeling technology for every step of the design process, allowing cross-domain information sharing to avoid guess-work and accurately predict the performance of the combined system.

Design needs for smart product enablement

The industry is in the middle of an “engineering renaissance” — one that is resulting in products that continue to enrich people’s lives by affecting the way they work, communicate, live, and travel. Phones, sensors, meters, cars, TVs, and many other devices that consumers use on a daily basis are now tagged with the phrase “smart.”

These smart devices monitor the environment, compute and predict people’s next steps, communicate their needs, and aggregate the information they seek. This interconnected ecosystem of devices has several key physical components: the end-device we directly use, the “cloud” through which these end-devices connect, and the communication link between these devices and the cloud.

Each of these three components has different design specifications and goals in terms of performance and requirements, but one common requirement that ties them together is the need for “power efficiency.” Power efficiency for the semiconductor chips that go into a handheld consumer device is an obvious design requirement to extend its battery life and to maintain its thermal signature within specific limits.

Power efficiency for chips that run the data-center equipment behind the cloud is also a key design requirement that is driven by metrics such as performance per unit watt. Integrated circuits (ICs), or parts of an IC, like the radio circuits or modem, for example, that enable chip-to-chip communication can drain a battery very fast if not designed with power efficiency from the beginning.

Power efficiency can be broken down into two broad categories: power budgeting and power delivery. Homes and offices are great examples to distinguish the two.

Power budgeting allows consumers to “reduce” the amount of power used through energy-saving appliances, motion sensor activated lights, LEDs, and more.

Power delivery, on the other hand, is the way that power is transferred from the generating stations to our homes, providing robust voltages for our appliances to operate by minimizing power delivery network (PDN) loss. If the transmission system is poorly designed, then power is lost in the network, which results in wild fluctuations of voltage at the end terminal.

The same concept applies to the smartphones. With more-power-efficient ICs, the demand of current from the battery will be significantly reduced and the battery charge will last much longer. Similarly, with the right design, package, and board, the supply voltage to the transistors and circuit will be stable.

Power-efficient ICs come from design flows that treat “power” as a design metric. One design flow that facilitates power budgeting for ICs comes from solutions that enables three key steps: power analysis, power reduction, and power regression, such as Apache Design’s PowerArtist register-transfer-language (RTL) power platform.

By using sophisticated and proprietary techniques that allow fast RTL-based analysis, accurate power estimates can be correlated to gate-level netlist power. Using early RTL power analysis permits designers to perform power debug in order to understand where they may have “power bugs” — design and logic constructs that waste power unnecessarily. Power regression allows monitoring and tracking of the design’s power signature through the design process, ensuring that it remains within its power budget.

Power consumption can be controlled through lowering the supply voltage at which the circuit operates, thus reducing the voltage swing needed to go from the “0” state to the “1” state (or vice versa). The reduced voltage swing results in a lower “charge” (charge = capacitance * voltage), and consequently a reduced current demand from the battery. Reduced supply voltage also results in lower heat dissipation that allows for smaller-form-factor designs and less stress on the cooling system.

However, a reduced supply voltage swing can have detrimental effects on the circuit’s performance as it significantly reduces the “noise margin” with which a circuit has in order to operate in a fail-safe manner. As the supply voltage reduces moving closer to the “threshold voltage” (when a circuit turns on or off), it becomes increasingly important to maintain the reduced supply voltage at a consistent level without too much fluctuation or degradation from its nominal or ideal value.

The goal is to design an electronic PDN that can transfer charge from the battery through the printed circuit board (PCB) and through the package and on-chip interconnects to the transistors — without degrading the voltage levels in a static (dc drop) or dynamic (transient swing) sense. The supply must be robust for various design operating modes and the transitions between them. This is critical because supply voltage degradation can cause chips to perform slower or even fail, and the end system stops working.

The electronic system PDN can be modeled as a network of resistors, capacitors, and inductors that come in the way of the transfer of charge from the battery to the logic circuit inside the chip. The PCB and package have “traces,” or interconnect routing, that provides the connectivity. The inductance in these traces dominates their resistance values. Typically the PCB, and sometimes the package, has discrete capacitors. The on-chip PDN structure is complex, with multiple networks or domains, each consisting of multiple layers of metal and via structures that connect the chip’s power supply pads to the transistors. The domains also have power-gates (or switches) that allow for saving leakage current during standby modes. Additionally, there is a significant amount of on-chip capacitance that comes from the CMOS devices or parasitic coupling between the on-chip interconnects. Figure 1a illustrates the various components that make up the entire electronic system PDN network.

A chip-package-system (CPS) approach for PDN design verification

Ensuring robust voltage levels for all operating modes of the circuit requires careful design and extensive simulations. A traditional divide-and-conquer design methodology in which a “voltage drop budget” is assigned to each of the design teams (chip, package, and PCB), and they in turn are expected to ensure they meet these limits creates several problem scenarios. The package and PCB cannot be designed in isolation and must account for the on-chip parasitics and the current drawn by the chip for various operating modes and transitions between them.

Approximations of the chip’s power using average power estimates, triangular, or step-function current profiles are often misleading and inaccurate. Similarly, the voltage drop inside the chip cannot be modeled without considering the package and PCB’s L and C, which have significant effects.

When design teams work in isolation and use lumped or approximate values, they generally “over-design” to compensate for known inaccuracies or else they will “under-design.” Over-design leads to increased system cost, while the latter causes the end system to not function properly.

Now, design engineers have access to a comprehensive suite of solutions to simulate the IC, the package, and the PCB individually and in a holistic manner. For example, ANSYS’ SIwave can be used to generate models of the package and PCB, which can be used by Apache’s RedHawk to perform system-aware full-chip dynamic power, noise, and reliability simulations (see Fig. 1b ). Similarly, RedHawk can generate an accurate and compact Chip Power Model (CPM) or Chip Thermal Model (CTM) that can be used to enable IC-aware system-level power and thermal analysis (see Fig. 1c ). This unified simulation-driven product development environment presents designers with the necessary toolkit to virtually identify and mitigate failure generating scenarios, allowing for cost optimization and first-time product success. ■