Lest you think there is nothing new with the august I2 C bus, let us dispel that notion. The first I2 C-bus-enabled ICs came out over 30 years ago, in 1982 from Philips Semiconductor as a simple serial bus to control various chips used in televisions. “I2 C bus” stood for “inter-integrated circuit bus.” Even though the history of I2 C is long, there are now many enhancements taking place, such as differential signaling to improve noise immunity and improved arbitration so it is easier to connect buses together.
The I2 C-bus is covered by an industry-wide specification that has gone through four major revisions. The most recent version was in 2012, with the bus now sporting operating speeds to 5 MHz, up from the original 100 kHz.
A quick review of history is in order. Revision 1.0 of the specification was released in 1992 and added a 400-kHz speed option. Version 2.0 from 1998 added High Speed mode and a number of power-saving options. The next major specification, in 2007, upped the operating speed to 1 MHz (Fast-mode Plus or Fm+). The last update to the spec, in 2012, introduced a unidirectional 5-MHz option called Ultra Fast-mode (UFm).
The I2 C bus has spawned many variations. Some of these name changes were due to patent protection afforded Philips Semiconductor on some of the key technologies of the bus. The original patents expired in 2004 and any trademark or intellectual property rights were transferred to NXP Semiconductor after a divestiture from Philips in 2006. The I2 C bus is the communication protocol for the ACCESS.bus, the VESA Display Data Channel (DDC) interface, the System Management Bus (SMBus), Power Management Bus (PMBus), and the Intelligent Platform Management Bus (IPMI).
Storied past and bright future
Why the interest in I2 C-bus protocols and interfaces? Nearly all IC sensors developed today use the I2 C bus as their communication channel. The simple two-wire interface saves on pin count and the efficient payload utilization ensures enough data bandwidth. Most importantly, the proliferation of I2 C-bus interfaces in microcontrollers makes hooking up these sensors easy — ensuring a wide application base.
Today's smartphone designs offer an interesting insight into the use of I2 C-bus devices. There are a large number of human and environmental inputs in modern smartphones: compass, gyroscope, altimeter, temperature, hygrometer, fingerprint, accelerometer, ambient light, proximity, haptics, grip, to name some. In all, there are more than 10 different I2 C-bus sensors in every smartphone design and the number is growing in each new platform upgrade.
The computing segment also relies on the I2 C bus. Server systems require the highest reliability and maximum up-time. The I2 C-bus offers an independent reporting structure for environmental values, including power supply voltages, current consumption, fan speeds, and temperature. In fact, there is an I2 C-bus channel connecting the memory DIMMs to the CPU to report on memory speed, configuration, and other operating parameters.
The I2 C-bus is used to connect a great many things.
What makes the I2 C-bus go?
With the increasing I2 C-bus speed and the growing number of peripheral chips, what are semiconductor manufacturers doing to make the bus even easier to use? A major issue is the different power supply levels in modern systems. The CPU uses the lowest voltage possible to minimize power consumption, while sensors use a higher voltage to increase the analog signal swing. Because of the different power supply voltages, the I2 C-bus requires a high-speed, bidirectional, robust, voltage level translator. Remember that the I2 C bus is bidirectional, but doesn't have a direction pin; the translator must detect which direction is being driven and adjust accordingly – not an easy task at high speeds.
In some cases, the I2 C bus must exit the relative safety of the equipment enclosure and present itself to the harsh and unpredictable outside world. Even inside the enclosure, long PCB traces may increase capacitive loading so signal rise times don't meet the specification. Both of these situations can be solved wih an I2 C buffer or signal amplifier. All of the design challenges of the voltage level translator remain with the buffer design, with the added need of high speed amplification.
Today's systems use a large number of I2 C peripherals and there is a chance of device address conflicts. The solution is a multiplexer chip that splits the upstream bus into two, four, or eight isolated downstream buses that act as independent segments. These segments can act as redundant branches or simply split the address space for the I2 C peripherals.
Next-generation directions for the I2 C-bus
NXP is actively engaged in improving and expanding the use of the bus. An issue that many people have is noise immunity. Although I2 C is highly reliable, there are no protocol methods to reject incorrect packets since the bus is designed to be simple and easy to use.
NXP is working on a hardware solution, sampling in the fourth quarter of 2013 which transparently converts the single-ended I2 C bus into a differential configuration. This greatly increases immunity to noise and overcomes any ground offset issues caused by different power supply domains. The protocol remains unchanged so existing software can be used.
The I2 C specification has provisions for multiple masters, but there are a number of areas which can cause issues. The NXP solution is aware of the protocol and what messages were sent before the arbitration was requested. This permits seamless switching between masters with no possibility of missed or malformed packets- increasing the reliability and safety of the entire system. Expect samples of the arbiter silicon in the first quarter of 2014.
Another area of development concerns multiple master arbitration. There are 127 I2 C addresses and each device has a base address hardwired into it. Many devices use pins to change the address, but many just have the one. Assume you have a device that only has one I2 C address, but must use four of them in your system. Then you use a multiplexer to split the upstream bus into four independent downstream buses. You can put the same I2 C address on each downstream bus with no conflict.
I2 C and SPI
The I2 C bus has been universally accepted because of the simple hardware and software needed to implement a working system. After years of “wringing out the system,” it seems doubtful that another bus could displace the venerable I2 C bus. SPI is often cited as a viable replacement. Because the interface is more digitally oriented it may seem simpler to design SPI into a system. But SPI is really only a hardware interface; the protocol is left completely open which means new software for each new SPI peripheral used.
The I2 C bus, on the other hand, is completely specified and all peripherals work with any master. However, the I2 C bus is analog intensive and does need careful system design to eke out optimum performance. We all owe it to ourselves to revisit the finer points of the I2 C bus and devote the design resources needed to maximize bus reliability. NXP is helping system designers by working diligently on IC solutions to meet next-generation design challenges and making easier for designers to achieve success.
Some chips
There are a number of level translators suitable for I2 C available. One example is the NVT200x family from NXP that feature one through five channels of level translation from 1 V up to 5 V or anything in between. The voltage translator devices don't amplify the I2 C signal; they only provide voltage isolation. An I2 C buffer appropriate for Fast-mode plus (Fm+) operation at 1 MHz is the PCA9617A with two independent power supplies and a propagation delay of less than 170 ns while amplifying the I2 C signal up to 30-mA drive strength for heavy capacitive loads or long cables.
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