TIming Requirements for Complex System Designs
Designing clock timing circuits for today’s high-speed systems is no simple task. Rising clock frequencies, shrinking timing margins, and tighter board layouts conspire to introduce new sources of skew, noise, crosstalk and other signal integrity issues. In many of today’s complex systems, designers must distribute multiple clocks around the board for a seemingly ever-expanding array of subsystems. At the same time, as clock networks grow in size and extend the length of transmission lines, designers must support differential signaling to minimize the effects of crosstalk and other forms of interference.
Designing clock-timing circuits for today’s high-speed systems is no simple task. Rising clock frequencies, shrinking timing margins, and tighter board layouts conspire to introduce new sources of skew, noise, crosstalk and other signal integrity issues. In many of today’s complex systems, designers must distribute multiple clocks around the board for a seemingly ever-expanding array of subsystems. At the same time, as clock networks grow in size and extend the length of transmission lines, designers must support differential signaling to minimize the effects of crosstalk and other forms of interference.
The stakes are high. As the highest speed and most widely distributed signal in the system, clock-tree circuits have a major impact on system performance, power dissipation, electromagnetic interference (EMI) and cost. If optimally implemented, they offer designers tremendous dividends in terms of efficiency, reliability and faster turnaround. If designers fail to efficiently design their clocking circuits, they can undermine the market success of their product. Historically, designers have relied on traditional oscillators, built from discrete components, to meet their clock tree design requirements. More recently, however, IC manufacturers have begun to offer a wide variety of silicon-timing devices designed to integrate some of these traditional timing functions into a single chip. This paper will review the challenges designers face today as they develop clock-timing circuits and examine how these different components can impact their design.
Read the rest of this article at:
http://www.idt.com/products/files/18380557/WP-TIMEREQ-00086.pdf?CFID=13318409&CFTOKEN=92381634
Advertisement
