1. Place the power decoupling capacitor as close to the IC as possible
Regardless of whether the conductor is a straight PCB track, it will exhibit inductance effects at high frequencies ― all conductors do. As a result, inductance will increase as the distance between an IC’s power-supply pin and its associated decoupling increases. Minimizing this distance reduces the likelihood of EMI and ESD effects.
2. Use a ground plane whenever possible
Ground planes reduce the electrical field strength within their vicinity, lowering the effect of radiated EMI on the performance of a circuit. Moreover, solid-copper planes create the lowest possible impedance path. Using this type of ground plan will ensure that all circuit ground points are at the same potential.
3. Use low-inductance capacitors for power-supply decoupling
Including capacitors with higher series inductance in your design runs the risk of lowering the circuit’s overall tolerance to ESD and EMI effects. This is because the effectiveness of capacitors at high frequencies is limited when used at higher values of series inductance by further adding to the series impedance of the capacitor. Seek to use ceramic surface-mount capacitors whenever possible, especially in place of electrolytic capacitors; this is because ceramic surface-mount typically offer low series inductance values.
4. Beware the effect protective gels and coatings may have on the PRT element
When gel or other protective coatings contact the diaphragm of a Piezo Resistive Transducer (PRT), they may causes a hysteresis effect that’s very difficult to correct by conventional sensor-conditioning techniques ― this reduces the sensor accuracy and repeatability. If protective coating cannot be avoided, then have a clear understanding of its properties in relation to temperature, mixing ratio variances, aging, and absorption.
5. Protect the IC during assembly
The device should be immediately discarded if the IC passivation layer was damaged during handling or assembly. Damage done to the passivation layer may transfer to the IC’s surface and cause device malfunction of failure down the road. A suspicion of damage is enough to warrant a rejection.
6. Ensure wiring between ASIC and PRT element is as short as possible
If the wires linking the ASIC and the PRT element are too long, they may act as an antenna, picking up stray signals. These in turn will cause poor sensor performance in brutal automative 2MHz-to-2GHz at-200-volts-per-meter EMI tests. One alternative solution is to use a ground plane for reducing noise. If this is not avaible, run grounded PCB tracks as close as possible to the sensor connection tracks, especially the connections to the conditioner inputs.
7. Select the proper PRT die attachment
The PRT die attachment required for optimal performance varies depending on the application. For low-pressure rear-pressure (less than 100 psi) designs and top-pressure designs, use an RTV. For rear-pressure designs greater than 100 psi, use epoxies. It is important to use a fluoro-silicon RTV because it prevents expansion caused by silicon oil absorption in oil-filled assembles.
8. ESD/EMI capacitors must be placed adjacent to the connector pins
Other factors that create ideal conditions for ESD and EMI include: exposed connector pins and the cable that connects with the actual unit; this cable can act as an antenna for picking up EMI. Fortunately, placing capacitors as close as possible to the connector will minimize the effect of conducted ESD and EMI on a circuit. Strive to link the capacitors between the connector pins and the case, guaranteeing that the pins and case are as far away as possible and at the same electrical potential at higher frequencies.
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