Today’s computing landscape

Today’s computing landscape

Meeting the challenges of mobile and cloud computing innovation

BY ROSS NELSON
General Manager
Digital Debug Solutions
Agilent Technologies
www.agilent.com

Ten years ago or even five years ago the personal computer industry was the driver of technical innovation. Desktops and laptops up-deployed technology to servers, and down-deployed technology into embedded and consumer products.

Today, technical innovation is driven by mobile and cloud computing. This innovation is feeding a worldwide industry that meets the demand for billions of mobile devices and the computing cloud that supports them. Innovation in size, power requirements, memory, battery life, and flexibility are the answer to the world’s thirst for small mobile devices that can do everything the desktop and laptop used to do, and even more. Add the huge increase in bandwidth now available via Wi-Fi and 3G/4G networks that is driving innovation in servers to enable the cloud.

Today’s computing landscape has shifted test and measurement needs as well. This innovation shift has changed the conversation around test and measurement needs to address designers’ debug and compliance test requirements.

The latest applications that consumers enjoy via their mobile devices every day, such as high-pixel still cameras with image processing/DSP, high-definition video, social media, GPS navigation and location services are driving tablet, smartphone, and other mobile device innovation at a furious pace. These mobile computing trends underscore the importance of:

• System performance: to manipulate photos, video, etc. requires significant system bandwidth and computational capability.

• Battery life and power management: system and connectivity bandwidth consume power, yet users expect all-day performance from their mobile devices.

• Connectivity bandwidth: App downloads, tweets, check-ins, etc. place demands on 3G/4G networks, but also on the internal buses, from the RF chip to the system-on-chip.

• Cost: The ubiquity of mobile computing puts a tremendous emphasis on cost due to the significant volumes.

• Size: To integrate these capabilities into a small form factor requires high levels of integration.

Servers that enable the cloud must keep pace with the demands of billions of smart device transactions in the hands of billions of consumers worldwide. In December 2011, IHS iSuppli had this to say about cloud computing:

“The cloud computing market is heading into the stratosphere as companies seek to offer services designed to serve tablets, smartphones and other mobile devices. …projected to surge to $110 billion in 2015, up from $23 billion in 2010.”

Device and application innovation

To address the advances in applications for mobile devices, major technology innovation is required inside these devices and inside the servers that support them, including low power high performance multicore SoCs or application processors on today’s most popular ARM and IA platforms. High-performance buses now come in a large variety for systems, displays, and I/O. Today there are many more buses to test and verify. Chief among these are the MIPI D-PHY and M-PHY multi-lane serial internal buses, which deliver high bandwidth at much lower power than traditional internal buses. For server computing, PCIe and DDR continue to evolve to deliver greater performance.

Table 1 underscores the difference between the requirements of a mobile computing device and a cloud server. For example, D-PHY, M-PHY and PCIe are all common internal physical layer buses. For a server computing application, PCIe 3.0 is the optimum bus because it delivers a maximum bandwidth of 8 Gbits/s. However, for a mobile computing device where power consumption is critical, a bus such as M-PHY, which delivers almost as much bandwidth (5.8 Gbits/s), is preferable because it consumes 1/20th of the power per bit (~10 pJ/bit).

Table 1. These power and performance specifications demonstrate the kind of innovation that is needed in mobile and server computing.

Advanced memory and connectivity

Relentless market forces have dramatically improved low-power memory systems. The mobile computing industry has seen the recent development of memory systems such as LPDDR, UFS, and UHSII. DDR4 and GDDR5 provide the very high speed and performance that servers require.

Mobile devices need access to high bandwidths and they require integration of the RF and digital functions. Cellular, Wi-Fi, Bluetooth, GPS, NFC, and RFID technologies require a high degree of integration and reliability to deliver data to mobile devices quickly and accurately.

Supporting design with new debug and validation tools

Figure 1 shows a typical mobile computing architecture; each block presents unique test and measurement design and validation challenges when compared with a traditional PC architecture.

Fig. 1: A typical mobile computing architecture, where debugging and compliance testing are critical to success.

With the latest low-power, high-performance, multicore SoC/application processors, insight into on-chip instruction execution and I/O is limited. No longer can a designer gain visibility through a front-side bus. New tools to trace on-chip execution via Embedded Trace Macrocell (ETM) and Program Flow Trace Macrocell (PTM) for ARM cores and proprietary tools for other architectures are needed.

New mobile computing buses such as MIPI are designed for low power by implementing different signaling methods. For example, D-PHY CSI2/DSI1 has a unique PHY that shifts from a low-power, single-ended 20-Mbit mode to a high-speed 1-Gbit differential mode. M-PHY CSI3/DSI2 has a bursty implementation with a power-saving idle mode that makes lane lock challenging at 5.8 Gbits/s.

Debug tools need to be able to track those signaling changes to effectively capture, display, and analyze the bus. Bursty buses such as M-PHY also create challenges in characterizing current drain and predicting the battery life. Greater dynamic measurement range (microamperes to amperes) is needed in power analysis tools to accurately measure the bursty current drain of mobile devices.

At data speeds exceeding 2.4 Gbits/s, capturing address, command, and data of DDR4 and GDDR5 server memory for debug and validation can be problematic. Memory technologies targeting mobile computing devices must provide adequate signal access. Developing effective probing techniques is critical to the validation process.

Other challenges include cross-domain debugging of digital and RF signals. Chasing issues from the air interface through the RFIC to the baseband IC across a digital IQ bus calls for tools that can acquire, display, and analyze across multiple domains, with support for multiple cellular standards and the DigRF v4 digital IQ interface. ■