Tool address low-power design challenges

The Eclypse low-power solution is offered as the most comprehensive suite of proven system-level, verification, implementation and signoff tools, intellectual property (IP), methodologies and services for low-power chip development. The solution enables design teams to adopt advanced low-power techniques while boosting productivity, reducing risk, and ultimately delivering high-quality silicon in an effort to meet or beat power, area, speed, and yield objectives.

Advanced low-power design techniques, such as MTCMOS power gating, multivoltage, and dynamic voltage and frequency scaling (DVFS), force a major shift in how engineers create and verify chips. Features include enhanced clock gating and low-power clock-tree synthesis, advanced multi-threshold leakage optimization, and automated power switch handling. In addition, the solution supports the industry-standard Unified Power Format (UPF) language, which is used to capture low-power design requirements. (Pricing based on configuration — available now.)

Synopsys , Mountain View , CA
Sales 650-584-5000
http://www.synopsys.com