Tool yields cost est. for 3-D IC fab operations
The TSV+ cost analysis tool aids development of ICs that use TSV (Through Silicon Vias) packaging technology. TSV can be used for 3-D integration of ICs, logic, RF-SiP, CMOS image sensors, and MEMS.
With the tool you can tune fab parameters: number of wafers per year processed, global process yield, number of working days per year, operator cost, engineer cost, etc. TSV+ will provide precise data on clean room (CR) class, CR maintenance cost, CR electricity consumption, CR amortization period, and equipment amortization periods. (Single-user license, 6,490 eurosavailable now.)
Yole Développement , Lyon , France
David Jourdan 011-33-(0)-472-83-01-80
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