TSMC Announces Power Trim Service for Advanced Chip Leakage Power Reduction

TSMC Announces Power Trim Service for Advanced Chip Leakage Power Reduction

Exclusively-licensed technology from Blaze DFM, Inc. enables design-specific leakage power reduction offering

Issued by: Taiwan Semiconductor Manufacturing Company Ltd.

Issued on: 2008/04/15

Hsinchu, Taiwan, R.O.C. – April 15, 2008 – Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced that it has signed an exclusive agreement with Blaze DFM, Inc. to offer Power Trim Service, a new service offering combining a patented Blaze power optimization technology with special variations of TSMC’s advanced manufacturing process.

Under the terms of the agreement, TSMC will make available to its customers the Power Trim Service which provides significant leakage power reduction while maintaining chip performance and area. In addition to delivering substantial reductions in leakage power above and beyond existing techniques already employed in the chip, the Power Trim Service also significantly reduces leakage power variability, a critical power issue to overcome in next generation system-on-chip (SoC) designs.

Meshing Designers’ Intent with Chip Manufacturing

The Power Trim Service is the first offering of its kind that blends a layer of design technology software with advanced semiconductor processing to tune the manufacturing process to the specific chip design. The Power Trim Service uses software developed by Blaze DFM that identify paths in the design that have sufficient timing “slack” and optimizes transistors along these paths without reducing the performance of the chip. The output of the software is a marker layer that identifies transistors for special handling during TSMC’s Optical Proximity Correction (OPC) process. The result of this special handling is to produce slightly slower transistors with significantly less leakage. While the leakage power reduction from adjusting an individual transistor is relatively small, when accumulated over the tens or hundreds of millions of transistors in a chip, the overall reduction is significant. This fine-grained optimization process results in substantially lower leakage power consumption for the entire design.

The Power Trim Service is fully compatible with, and may be used in conjunction with, all other leakage reduction techniques such as multi-Vt cell libraries, reverse body biasing, header/footer sleep switches, and voltage islands. It provides additional leakage improvements over and above what can be achieved with these other techniques.

The Power Trim Service does not require any major changes to the customer’s existing design flow, design signoff, or hand-off to manufacturing. It does not require any existing design tools to be replaced, and does not require any changes to the chip architecture, cell libraries, intellectual property blocks, logic design, or physical layout.

Advantages of Power Trim Service

TSMC has validated the power saving benefits of Power Trim Service on internal and customer designs. The Power Trim Service has been proven to deliver sizable reductions in average leakage power and significant impact on leakage variability on cell-based digital design. The corresponding increase in parametric yield can mean substantial cost savings.

Two of the top five fabless semiconductor companies have already fabricated chips with this process option at TSMC and others are being added selectively during a phased rollout of the technology.

“Power leakage has long been an issue for IC designs, especially in the smaller geometries,” said Fu-Chieh Hsu, vice president of Design & Technology Platform at TSMC. “With the Blaze DFM technology, we now have a tool that discovers areas for optimization that was not previously possible. This means we can provide customers with the ability to minimize power leakage problems, thereby saving their time and money to meet the market demand.”

“TSMC has produced exciting results for our mutual customers during the silicon validation process,” said Jacob Jacobsson, CEO of Blaze DFM, Inc. “Now customers can have easy access to our patented technology directly from TSMC as part of TSMC’s Power Trim Service. This is just the first of several technologies that Blaze intends to bring to the market by leveraging our unique position at the design to manufacturing handoff and our partnership with TSMC.”

Availability

The Power Trim Option is available directly and exclusively from TSMC for TSMC advanced process technologies including 90nm, 80nm, 65nm, 55nm, and 45nm process nodes and for select TSMC customers during the initial introductory period. Customers will not be required to separately purchase or license any software from Blaze. Blaze technology is exclusively embedded in the Power Trim Service offering. Interested customers should contact their TSMC sales representative for more information.

Financial terms of the agreement between TSMC and Blaze were not disclosed.

About Blaze DFM

Blaze DFM provides software solutions to fabless semiconductor companies, integrated device manufacturers, and silicon foundries. Blaze products give IC designers greater control over manufacturing variability, improving yield and shortening time to volume production. Blaze DFM, Inc., 1275 Orleans Drive, Sunnyvale, CA 94089, 408.470.4900, www.blaze-dfm.com

About TSMC

TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2007 exceeded eight million (8-inch equivalent) wafers, including capacity from two advanced 12-inch Gigafabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.