Verification tool adds numerous checks

Ascent Lint Version 1.3 early functional verification tool adds VHDL checks, as well as checks for ambiguous modeling. The tool also shows the differences between simulation and synthesis semantics.

The software performs syntax and semantic Hardware Description Language lint checks for today’s complex SoC designs and features an extremely fast engine and low noise report. The package supports naming and RTL coding conventions, VHDL subset restrictions to enforce modeling clarity and reduce complexity, and network and connectivity checks for clocks, resets, and tristate-driven signals. (From $25,000 — available now.)

Real Intent , Sunnyvale , CA
Sales 408-830-0700

http://www.realintent.com