Verilog 2001 simulator is really low cost

For a limited time, SynaptiCAD will be giving away free, no strings attached, six-month licenses for VeriLogger Extreme. a high-performance compiled-code Verilog 2001 simulator that reduces simulation debug time. The full package of both Linux and Windows versions will be available.

The software provides both RTL and gate-level simulations with SDF (Standard Delay Format) timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx. The user inputs ZVerilog model code, draws waveforms for stimulus, and views waveform results. The package is normally $4,000 per user/year. (No cost — available now.)

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