Verilog design tool supports encrypted IP

VeriLogger Extreme, a compiled-code Verilog simulation and debugging environment, now features support for encrypted IP models from all the major ASIC/FPGA vendors. The package supports both binary-encrypted SmartModels based on the common SWIFT-based standard and the more recent encrypted source-code format (protected envelopes) added as part of the Verilog-2005 standard.

Available in Linux and Windows versions, VeriLogger Extreme offers fast simulation of both RTL and gate-level designs with SDF timing information. It supports design libraries and design flows for Actel, Altera, Atmel, LSI Logic, QuickLogic, Xilinx, and major ASIC vendors. Free 6 mo. trials licenses are being offered. (From $4,000 – available now.)

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