RP-HL3.MAY
VHDL simulation takes leap forward
Next generation of simulator technology improves speed from two to 10
times
With designs growing ever more complex, the speed with which they can be
simulated becomes an increasingly critical issue. A breakthrough based on
compiled-code technology promises to remove some of the performance
barriers associated with using the Very High Speed Integrated Circuit
Hardware Description Language (VHDL.)
Software VHDL simulation is about to become a lot faster. Based on a
technology breakthrough involving the way in which VHDL models are
translated into machine code, two new VHDL simulators–V-System from Model
Technology, Inc.and Leapfrog from Cadence Design Systems, Inc.–are being
offered as performing at speeds typically two to 10 times faster than
other such products. The simulators are addressing the part of the VHDL
design process that has become the major bottleneck in top-down
design–simulation performance at the behavioral/RTL (register transfer
level). According to Tony Zingale, vice president and general manager of
Cadence's HDL Design Group, “This announcement fundamentally changes
simulation as we know it.” Slow simulation performance has caused many
potential users either to forego the advantages of using VHDL or to invest
in expensive server and accelerator hardware. Now, says Dr. Robert Hunter,
president of Model Technology, users of his company's product “can rapidly
iterate on their designs using the computer on their desk.” VHDL
simulation involves several basic steps: compilation, simulation, and
debugging. Before VHDL source code can be simulated, it must be compiled
or translated into machine object code for the host CPU to execute. Once
it is executed, simulation results are displayed. The results are analyzed
and the design is debugged. If changes need to be made, the process must
be repeated. Previous VHDL simulators have used one of two approaches:
interpreted or C-Compile. With the interpreted approach, a VHDL model is
translated, or parsed, into a stream of data that is interpreted by a body
of code as a sequence of synthetic instructions. A single common simulator
program usually executes all models. With the C-Compile method, a VHDL
model is translated into a C program, which is compiled to produce a
module that can be linked to other modules, as well as a support kernel.
The resulting program is the simulation. Each separate simulation may
imply a unique executable program. Interpreted simulators have the
advantage of delivering superior VHDL compiler performance. On the other
hand, C-Compile simulators offer faster simulation execution. However,
both approaches involve tradeoffs that prevent VHDL performance from
reaching its theoretical maximum. The new approach–referred to by
Cadence as the native-code approach and by Model Technology as Direct
Compile–combines the advantages of the interpreted and C-Compile methods,
with none of the tradeoffs. In this method, the intermediate
representation of a VHDL model produced by the parser is processed by a code
generator that directly produces relocatable machine code, which is
directly executable by the CPU. By avoiding the use of the platform's
software, significant time is saved in setting up the simulation run. In
addition, fixed size restrictions on designs processed are eliminated and
greater optimization is allowed. The method's main disadvantage involves
the complexity of the code generator, which explains why this approach has
not been used in earlier simulators. The Leapfrog simulator (see Fig. 1)
is offered as providing users with full 1076-language support and a
complete simulation environment. The simulator includes an enhanced
graphical user interface, language-sensitive editor, design library
manager, source code debugger, and flexible waveform and data display
tools. Leapfrog works with the company's mixed-level design composition
environment and the Synergy family of synthesis tools. The simulator will
also work with Cadence's ASIC Workbench as well as interface with the
Verilog-XL simulator. The initial release of Leapfrog will be available on
Sun SPARC-based platforms in the second quarter for $43,750 for a floating
license. The V-System simulator (see Fig. 2) also fully conforms to the
IEEE standard 1076 for VHDL and interactive source-level debugging. It
features a Structure View window that provides a complete road map of a
design, letting users navigate anywhere in the design hierarchy at any
level of detail. Structure View is dynamically linked to seven other windows
that offer multiple views into the design, including a display of VHDL
signals as familiar waveforms. V-System is available for Windows on IBM
PCs and compatible computers as well as on Unix workstations, including
the HP Series 700, IBM RISC System/6000, and Sun SPARCstation models.
V-System for Windows is $2,495 for a single copy; V-System for Unix is $9,
995 for a single floating license. For more information on V-System, call
Bob Hunter at Model Technology at 503-690-6838 or circle XXX. For more
information on Leapfrog, contact Mike Sottak at 408-428-5036 or circle
XXX. –Richard Pell Jr.
captions to come
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