VHDL verification tool is open source

An open-source constrained random verification software package that uses VHDL-200 or -2008 is available for download. The free package offers a proven methodology and allows VHDL design and verification engineers to add constrained random testing to their existing VHDL testbenches — all done in VHDL.

Constrained random testbenches create tests by successively randomizing sequences (transactions or groups of transactions) that are valid for a particular environment. The company providing the tool, SynthWorks, focuses primarily on offering VHDL training courses. See www.synthworks.com/downloads. (No charge — available now.)

By Jim Harrison

SynthWorks Design , Tigard , OR
Jim Lewis 503- 590-4787

www.synthworks.com