Virage Logic Expands Silicon Proven 40-Nanometer Embedded Memory and Logic Library IP Portfolio to Low Power P

Virage Logic Expands Silicon Proven 40-Nanometer Embedded Memory and Logic Library IP Portfolio to Low Power Processes

SiWare(TM) Memory and SiWare(TM) Logic Physical IP Provides Built-in Power Management Capabilities to Help Meet Stringent Power Budgets

FREMONT, Calif., Dec 16, 2008 (BUSINESS WIRE) — Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry’s trusted IP partner, today announced the expansion of its silicon proven 40-nanometer (nm) embedded memory compiler and logic library product portfolio with new availability for low power (LP) processes. The expanded SiWare(TM) product portfolio provides semiconductor companies with 40nm physical IP that is designed to enable Systems-on-Chip (SoCs) to run faster, manage power more efficiently, use less area, and achieve higher manufacturing yields. The SiWare product line, first introduced in October 2007 for the 65nm process node and in April 2008 for the 40nm process node, addresses the increasingly complex design requirements placed on physical IP at advanced process nodes. The SiWare Memory compilers and SiWare Logic libraries provide designers with a complete “dashboard” of options, including built-in power management capabilities, for maximum flexibility in effectively managing design tradeoffs to meet specific requirements at this advanced process node. The SiWare power management capabilities support techniques, such as Dynamic Voltage Frequency Scaling (DVFS), as well as multiple power management modes including light sleep, standby and hibernate.

“Our SiWare 40nm general process customers have enjoyed early access to design more competitive chips at reduced risk while helping enable them to take advantage of significant cost savings,” said Brani Buric, executive vice president of marketing, Virage Logic. “By expanding the availability of the SiWare product line to include low power processes, customers designing for end markets such as wireless, battery-operated and consumer applications can take advantage of the product line’s advanced power management capabilities. With static power savings of up to 35 percent, 70 percent and 95 percent, depending on the selection of the built-in power management modes available in both the 40nm general and low power memories, we believe this provides our customers with a competitive advantage.”

About Virage Logic’s SiWare Memory Compilers and SiWare Logic Libraries

The SiWare Memory product line of silicon aware compilers provides power-optimized memories for advanced processes at 65nm and 40nm. These high-performance memory compilers minimize both static and dynamic power consumption and provide optimal yields. SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area. SiWare High-Speed memory compilers are designed to help designers achieve the most aggressive critical path requirements. Compile-time options for power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.

The SiWare Logic product line includes yield-optimized standard cells for a wide variety of design applications at 65nm and 40nm with multiple threshold process variants. SiWare Logic libraries are offered using three separate architectures to optimize circuits for Ultra-High-Density, High-Speed, or general use. SiWare Power Optimization Kits provide designers with advanced power management capabilities.

Availability and Pricing

Silicon proven SiWare Memory compilers and SiWare Logic libraries are available now. Project pricing starts at $100,000. The SiWare product portfolio supports all major electronic design automation (EDA) tool flows targeted for the 65nm and 40nm process including Cadence Design Systems, Magma Design Automation and Synopsys. For specific foundry availability, please contact info@viragelogic.com. ■