VMM methodology speeds SystemVerilog verification

VMM methodology speeds SystemVerilog verification

Package boosts productivity for developers of ASICs, SoCs, ASSPs, and FPGAs

Engineers developing complex high gate-count ASICs, SoCs, ASSPs and FPGAs are increasingly using IEEE Standard 1800-2005 SystemVerilog for all-important productivity and time-to-market gains. The next-generation VMM methodology provides engineers with architecture guidelines and industry best practices that enable more effective and faster functional verification using SystemVerilog. It gives higher verification productivity with three new components: VMM Planner, VMM Applications, and VMM Automation.

VMM Planner extracts and rolls up a variety of verification results such as code and functional coverage, formal and dynamic assertions, and test pass/fail data into an annotated plan that can be shared as an accurate and objective assessment of verification progress; VMM Applications reduces testbench creation time by allowing architects to quickly construct more effective verification environments; and VMM Automation improves the productivity of engineers developing and using advanced testbenches. The VMM methodology is a part of the VCS functional verification solution and Pioneer-NTB testbench automation tool. ($12,900/yr for a globally WAN-able license—Planner and Applications beta version available now; Automation tools available in 12 to 24 months.)

Synopsys , Mountain View , CA
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