Working with boundary-scan test

MS96.JAN–Advanced Micro Devices–rm

Working with boundary-scan test

Boundary-scan builds testability into the circuit, a must as designs
become increasingly complex

BY LINDA BISHOP Advanced Micro Devices, Inc. Sunnyvale, CA

The ever-increasing complexity of integrated circuits, high-pin-count
surface-mount packages, and shrinking printed-circuit boards have made it
difficult to test such designs using bed-of-nails and mechanical probes.
The greater complexity of ICs also makes it harder to generate tests that
will exercise them fully from the pc-board edge. Test data must propagate
through several chips to reach those at the center of the board, making
longer test sequences necessary. Boundary-scan test (BST) is a different
approach to debugging and testing. BST adds test electronics to every I/O
pin. Boundary-scan confirms that each component within an IC or on a
pc-board edge does what it should and that the components are
interconnected correctly. It also functionally tests the completed
product. The IEEE 1149.1-1990 Joint Test Action Group (JTAG) standard can
be applied to boards, modules, or systems. BST allows testing by means of
a built-in four- or five-pin test bus accessing input and output pins.
BST creates a strong link between design and test. The onetime BST
investment can be used to diagnose a fault in the design phase,
manufacturing phase, or field service of the product. BST thus lowers
manufacturing costs and reduces the cost of test program generation. BST
is currently used in ICs and pc-board designs. Boundary-scan ICs are
available from such companies as Advanced Micro Devices, Analog Devices,
Fujitsu, Motorola, the Mips silicon partners, National Semiconductor, and
Texas Instruments. Many microprocessors offer on-chip emulation features
that are controlled by the boundary-scan port. BST could be expanded in
the future to include such features as software testing, IC verification,
timing analysis, and environmental testing.

What is boundary-scan? The boundary-scan technique as outlined in the
IEEE 1149.1 specification puts a shift register (contained in a
boundary-scan cell) between the core logic and the input and output
buffers adjacent to each component pin (see Fig. 1). This configuration
allows signals at each I/O pin to be controlled and observed. The
boundary-scan cells of a component are connected in a shift-register chain
(which constitute a boundary-scan register). A test data input and test
data output connection along with control signals and clocks make up a
test access port (TAP). Test data shifted through the boundary-scan path
via the TAP will reach each test node. During normal operation, data pass
between pins and logic as if the boundary-scan cells were not there. In
test mode, however, a test program can direct the boundary-scan cells to
pass data along the shift@MDIN-register path. If all the component I/Os
used in a circuit or pc-board edge have a boundary-scan cell, then the
resulting serial path through the design enables component interconnect testing or individual IC testing. Boundary-scan tests can detect many of the
faults that in-circuit testers address, but without bed-of-nails or probe
access.

BST tests External interconnect and cluster testing shifts test data via
the TAP into all the cells associated with output pins and captures the
response in the cells associated with input pins. This procedure can
reveal opens, shorts, and cluster failures (see Fig. 2a). An internal
self-test can be performed by isolating on-chip system logic from
surrounding stimuli. Sampling and examination of all I/O signals can also
be performed without the operation of the on-chip logic. This test can
identify missing, wrong, or dead ICs (see Fig. 2b).

Boundary-scan architecture The boundary-scan architecture has four
elements: the TAP, a TAP controller, an instruction register, and a group
of test data registers (see Fig. 3). The instruction and test data
registers have separate shift-register-based access paths connected in
parallel between test-data-in (TDI) and test-data-out (TDO) pins. The TAP
controller selects paths. All signals pass through the boundary-scan cell.
The boundary-scan cells are controlled by signals from the TAP. The TAP
has at least three input connections: TDI, test clock (TCK), and test mode
select (TMS). The TAP also has one output connection: TDO. An optional
input, connection test reset (TRST), can asynchronously reset the test
logic. All IC input and output signals shift in and out via the serial
TDI/TDO path. The TAP controller is controlled by the TMS and TCK obtained
from a system level bus or automatic test equipment (ATE). It generates
clock and control signals for the instruction, boundary-scan, and bypass
registers (see Fig. 4).

Test access port The TCK input allows the serial test data path between
components to be used independently of system clocks, which may vary
between components. The TCK also ensures that test data can be moved to or
from a chip without changing the state of the on-chip system logic. The
TCK is driven by the ATE. If the TCK must be stopped (for instance if the
ATE must retrieve data from external memory and is unable to keep the
clock running), it can be stopped at zero or one indefinitely without
causing any change to the state of the test logic. To ensure race-free
operation, changes on the TAP's TMS input are clocked into the test logic
and changes on the TAP's TDI input are clocked into the selected register
on the rising edge of TCK. The contents of the selected register shift out
on TDO on the falling edge of TCK. The TAP controller has 14 possible
states. They determine what happens on the next clock (see box, “TAP
controller states”).

Registers The elements making up the architecture include the
instruction register and a group of test data registers (TDRs). These
registers have separate shift-register-based serial access paths,
connected in parallel between the TDI and TDO pins. Selection of the paths
is made by the TAP controller (see Fig. 5). The instruction register is a
serial-in parallel-out register that determines the test to be performed. It
includes two shift-register-based cells for holding instruction data. The
architecture includes at least two TDRs: a bypass register and
boundary-scan register. A third register, the device identification
register, is optional. Each TDR is addressed by an instruction scanned
into the instruction register. The bypass register is a single-stage
shift register providing a single-bit serial connection through the
circuit when none of the other TDRs is selected. This register can be used
to allow test data to flow through a device to other components in a
product without affecting the normal operation of the device. For
example, if a pc board has 30 IC components with an average component
register length of 100 stages then the total serial path length through
the board is 3,000 (remember the boundary-scan registers are connected
into a serial chain). If only one IC is to be tested on the board, the
other 29 ICs can be bypassed. Thus only 129 stages (100 stages plus 29
bypass stages) are required instead of 3,000. This bypassing feature
reduces testing time considerably. The boundary-scan cells that
constitute the boundary-scan register are arranged to form a scan path
around the boundary of the core logic. These cells are connected between
each digital system pin and the on-chip system logic. Using these cells,
the boundary-scan register can control and observe the state of each
digital system pin. The boundary-scan register allows IC interconnect testing, IC self-testing, and sampling of input and output signals without
interfering with the operation of the on-chip logic. The BSR can also
remain idle showing no load to the on-chip logic. Figure 6 shows a
standard boundary-scan cell. The device ID register is optional and can
provide binary information about the manufacturer's name, part number, and
version number of the component. This allows, for example, verification
that the correct IC has been used in the proper place on a pc-board edge
and device version number verification. Instructions for the registers
include public and private instructions. Private instructions are
documented by the manufacturer allowing access to specific test features.
Public instructions are defined by the IEEE 1149.1 specification (see Fig.
7).

Public instructions This section needs a short introductory paragraph.
EXTEST. For board level interconnect and logic tests. Allows the TAP to
drive outputs and sample inputs. INTEST. Used to test internal logic.
Allows a Hardware Development System to drive the circuits test interface
without a direct electrical connection to all pins of the package.
SAMPLE. Tests external signals without interfering with system operation.
BYPASS. Bypasses the boundary-scan register and shortens access times to
other devices at the board level. Advanced Micro Devices has implemented
this standard on the Am29030 RISC microprocessor and Am29200 RISC
microcontroller. In addition to the public instructions in the standard,
private instructions in the 29200 assist hardware development with simpler
tools than a full in-circuit emulator.

BST tools Boundary-scan testing does not always eliminate the need for
other forms of testing. Soon, very few pc-board edges will be built
exclusively with boundary-scan components. Thus a dual test strategy is
necessary for mixed-technology pc-board edges. Testers must be able to
examine both boundary-scan and non-boundary-scan devices. Boundary-scan
testing can be used wherever possible. The remaining parts can be tested
using a cluster test via the boundary-scan parts, or using traditional
test methods, such as MDA, in-circuit test, or functional test. The
overall test cost will be significantly lower than without any
boundary-scan devices. Boundary-scan interconnect diagnosis requires
complicated software not found in digital testers. A boundary-scan tester
also must be able to analyze the fault data in software rather than
relying on a fault dictionary. Several manufacturers make logic analyzers
and board test systems with this capability. These manufacturers are also
developing the software for generating test vectors and for running the
logic analyzer. Eventually, use of the IEEE BST standard will allow
testers to be no more than small computers equipped with the appropriate
software and a hardware plug-in. Most currently available boundary-scan
testers consist of three elements: the boundary-scan adapter box, test
vector generation software for a PC, and diagnostic software running on
the logic analyzer. The adapter box contains the connections to the TAP.
The first step in BST is to develop the test vectors. First, a net
assignment file is created on a PC containing the netlist information for
the circuit and the boundary-scan chain. The pattern generation software
automatically generates the BST vectors for interconnect testing. These
are then loaded into the logic analyzer. The logic analyzer is then
connected to the circuit via the TAP port. Using simple menu commands, the
boundary-scan tests can now be executed.

Mixed-technology test scenario IC manufacturers are just beginning to
offer boundary-scan versions of popular devices, and although many new
component designs do support boundary-scan, pc-board edge manufacturers
will be slow to adopt this technology. Thus it is necessary to define a
test strategy for pc-board edges with a mixture of boundary-scan and
conventional components. In the example shown in Fig.8 the pc-board edge
contains a group of boundary-scan components tied together on one scan
path via the TDI/TDO pins and a group on conventional components with
tester access. There is no access to the nodes that interconnect the
boundary-scan components. First, a traditional in-circuit shorts test is
run to detect any shorts between probed nodes. Next a boundary-scan
hardware test is run to check if the correct boundary-scan circuitry is
functional and that the correct boundary-scan components are properly
placed. This test checks that the TAP nodes (TDI, TDO, TMS, and TCK) can
be driven high and low and are not stuck at a given value or shorted to
other nodes. This test also checks that the boundary-scan, bypass, and
instruction registers can be loaded. The more probes used on the scan
path, the better the diagnostic resolution of this test. For example, if
you probe only the TDI pin and the last TDO pin in the scan path you can
determine only where the first fault in the scan path is located. By
probing the TDI/TDO between each component you can determine all problems
in the testability hardware. This procedure also allows you to locate
shorts between scan path nodes and other nodes. Following the
boundary-scan hardware test, a boundary-scan Opens test is performed. This
test checks for open pins on each probed boundary-scan component node on
the pc-board edge. This test will find opens for a variety of defects
including a break in the pc-board edge track, a bad solder joint, a
unconnected component, or a broken bond wire. A major advantage to the
boundary-scan opens test over conventional in-circuit tests is that there
is no need to understand the internal system logic. With a conventional
in-circuit test you must apply numerous test vectors to the input pins and
enable a path through the logic so the state of each pin can be observed
at an output pin. The boundary-scan test allows the designer to directly
control the values driven on the output pins and observe the values on the
input pins. Next an Interactions test is run to check for shorts between
nonprobed boundary-scan nodes and probed conventional nodes. First, using
the EXTEST instruction, the outputs of all the boundary-scan components
are driven to a 1, and the associated boundary-scan inputs pins are
observed for those 1's. Thus all boundary-scan nodes have a known state.
Then using a tester probe, each non-boundary-scan node is driven high (1)
then low (0). Any problems will thus be detected as shown in Fig. 9.
Last, a boundary-scan Interconnection test is run, again using the EXTEST
instruction, to check for shorts and opens at boundary-scan to
boundary-scan nodes. Here tester probes are only needed for boundary-scan
nodes that run off the pc-board edge. Test patterns are shifted into the
boundary-scan cells at chip output pins and driven onto the board level
interconnections. The responses that arrive at chip inputs are loaded into
their boundary-scan cells and shifted out for examination. Careful
selection of the applied test patterns allows chip-to-chip connections to
be tested for stuck at, shorts, and opens. Suppose that a circuit
contains a short-to-ground and a wired-OR short-circuit fault (see Fig.
10). Using the EXTEST instruction two test patterns are applied. Each is
shifted into the boundary-scan registers separately, with the rightmost
bit shifted in first. The expected responses, which are shifted out as the
next test pattern is shifted in, (right most bit shifted out first)
differs from the expected response indicating a fault. Using
boundary-scan components has a significant impact on test generation. Very
complex ICs require hundreds of thousands of test vectors, boundary-scan can
obtain 100% opens and shorts fault coverage, however, with only a few
hundred. This technique greatly reduces test execution time. In addition,
the boundary-scan model may already be available from the design phase,
reducing production test set-up time. And by using boundary-scan testing,
process faults can be detected during the manufacturing process.
boundary-scan thus produces a strong link between design and test and can
play a large part in reducing a product's time to market.

Box 1

TAP controller states The TAP controller, a simple finite-state machine,
performs different functions depending on the setting of four bits in its
state register. Two unassigned states could be used for chip-specific
extra functions: Test-Logic-Reset. Test logic is disabled so all on-chip
logic operates normally. Run-Test/Idle. State between scan operations.
Activity in selected test logic occurs only when certain instructions are
presented. Capture-DR. Data is parallel loaded into Test Data Registers
from parallel inputs. Update-DR. Shifting process is complete. Test Data
Registers may be provided with a latched parallel output preventing the
parallel output from changing while data is shifted into the associated
shift register path. Shift-DR. Previously captured data is shifted
between TDI and TDO one shift register stage. Capture-IR. The Instruction
Register is parallel loaded into the shift register stage of the
Instruction Register. Shift-IR. Previously captured data is shifted between
TDI and TDO one shift register stage. Update-IR. Instruction data is
loaded from the shift register into the parallel output of the Instruction
Register. The new instruction, once latched, becomes valid. Pause-DR.
Temporarily halts the shifting process. Pause-IR. Temporarily halts the
shifting process. Exit1-DR/IR. These states are used to determine the
route to be followed in the state diagram. Exit2-DR/IR. These states are
used to determine the route to be followed in the state diagram.
Select-DR-Scan. These states are used to determine the route to be
followed in the state diagram. Select-IR-Scan. These states are used to
determine the route to be followed in the state diagram.

CAPTIONS:

Fig. 1. Each boundary-scan IC can capture data, update data, or serially
shift data to its neighbor (a). Within a pc board assembled from several
ICs (b), the boundary-scan registers for the individual components can be
connected to form a single path through the design. A board design could
also contain several independent boundary-scan paths.

Fig. 2. An interconnect test can reveal opens, shorts, and cluster
failures (a). An internal IC test can identify missing, wrong, or dead
ICs.

Fig. 3. The boundary-scan architecture has four elements: the TAP, a TAP
controller, an instruction register, and a group of test data registers.

Fig. 4. With all boundary-scan registers connected in series on a
pc-board, the TMS and TCK can be connected in parallel to each IC while all
test data pins (TDI and TDO) are connected as a daisy chain to form a
single path at the pc board level (a). With two parallel test paths, a
pc-board configuration can be in parallel, using a pair of coordinated TMS
signals to ensure that only one serial path is scanning data at a given
time. This setup can be controlled so that one path is tested at a time

Fig. 5. The TAP controller selects the separate shift-register-based
serial access paths.

Fig. 6. The TAP can access, affect, and sample inputs and outputs because
a boundary-scan register and Parallel Data register are incorporated into
the design.

Fig. 7. How instructions work.

EXTEST: 1. Latch input values in boundary cells. 2. Shift latched
values around to TDO and out; shift new values to output pins just
following. 3. Drive the inserted values on the output.

INTEST: 1. Latch internal data on output scan cells. 2. Shift a new
test vector in TDI and shift the captured values out the TDO. 3. Send the
input test vector into the internal logic.

Fig. 8. The pc-board edge contains a group of boundary-scan components
tied together on one scan path via the TDI/TDO pins and a group on
conventional components with tester access.

Fig. 9. Using the EXTEST instruction, the outputs of all the
boundary-scan components are driven to a 1, and the associated
boundary-scan inputs pins are observed for those 1's. Thus all
boundary-scan nodes have a known state. Then using a tester probe, each
non-boundary-scan node is driven high (1) then low (0).

Fig. 10. Using the EXTEST instruction two test patterns are applied. Each
is shifted into the boundary-scan registers separately, with the rightmost
bit shifted in first.

Box 1 figure: The value shown adjacent to the state represents the TMS
signal level at the time of a rising edge of the TCK. All state
transitions occur at the rising edge of the TCK pulse.