Using 40-nm process technology, the PSoC 6 combines ARM Cortex-M4 and Cortex-M0+ processor cores in a single chip along with a substantial array of system resources. The dual-core architecture enables power-saving system designs in which the lower-power auxiliary core serves as an offload engine, allowing the main core to sleep. The software-defined peripherals provide developers with flexibility to create optimized designs.
Active power consumption in the PSoC 6 is as low as 22 µA/MHz for the main processor and 15 µA/MHz for the auxiliary core. The Cortex-M4 operates to 150 MHz, while the Cortex-M0+ operates to 100 MHz. Integrated PLLs and an onboard buck converter and LDO regulator allow the device to implement dynamic voltage and frequency scaling so that developers can further tune its operation for their specific needs.
The PSoC 6 peripheral set is flexible, allowing software definition of their individual functions and creation of custom analog front ends. Available peripherals include op-amps and comparators, 12-bit DACs and ADCs, serial communications blocks, serial memory interfaces, and both 16- and 32-bit counter/timers. The devices also offer an integrated Bluetooth 5.0 radio, a capacitive touch sensor interface, and SRAM with DMA.
For IoT security, the PSoC 6 provides a trusted execution environment with secure boot. It also offers a cryptographic accelerator capable of handling elliptic curve cryptography, AES, secure hash independent of the main processor, and secure storage.
The PSoC Creator tool supporting the SoC is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling, and debugging of PSoC systems. Applications are created using schematic capture and over 150 pre-verified, production-ready peripheral component configurations.
Advertisement
Learn more about Cypress Semiconductor
